Multi-channel clock buffer test system and method

Abstract

The invention discloses a multichannel clock buffer test system and method, and relates to the technical field of semiconductor testing, and the method comprises the steps: calibrating the delay of an optical clock signal of each time-to-digital converter node to a preset precision threshold value; a standard clock signal is injected into the clock buffer input channel, and the clock buffer is driven to enter a working state; triggering a time-to-digital converter array by using the calibrated optical clock signal, collecting timestamp data of each output channel of a clock buffer, and generating an original time data set; inputting the original time data set into a double-mixing processor, and outputting a multi-channel skew parameter and a three-dimensional cloud picture; the multi-channel skew parameter is converted to a life indicator value for each output channel of the clock buffer based on the multi-channel skew parameter invoking a material model. According to the invention, the original time data set is subjected to two times of frequency mixing processing through the double frequency mixing processors, and phase detection and spectrum analysis are combined, so that high-precision extraction of the time deviation value of each output channel of the clock buffer is realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and in particular to a multi-channel clock buffer testing system and method. Background Technology

[0002] In optical communication and high-speed digital systems, the stability and timing consistency of clock signals are key factors in ensuring overall performance. With the continuous improvement of data transmission rates, multi-channel clock buffers, as core devices for achieving high-precision clock allocation, are widely used in key fields such as high-performance computing, 5G communication, and optical modules. Traditional testing methods usually rely on general-purpose instruments such as oscilloscopes or time interval analyzers to obtain skew parameters by comparing channels one by one. This method is limited by equipment bandwidth and synchronization accuracy, making it difficult to meet the needs of multi-channel parallel testing, especially in ultra-high-speed scenarios, where its measurement efficiency and resolution have significant bottlenecks.

[0003] In existing technologies, some solutions employ differential measurement structures based on a fixed reference clock to improve measurement consistency and repeatability. However, these methods do not fully consider the impact of inherent time delay differences between measurement nodes, making it difficult to further compress the overall measurement error. In addition, traditional testing procedures typically lack modeling of the relationship between clock skew and device material properties, making it difficult to assess the long-term stability and reliability of devices from a physical mechanism perspective. All of these limitations restrict a comprehensive understanding and accurate prediction of the performance of multi-channel clock buffers. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a multi-channel clock buffer testing method to solve the problem of lack of modeling correlation between clock skew and device material properties.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a multi-channel clock buffer testing method, which includes,

[0008] The optical clock signal is distributed to the time-to-digital converter array, the optical clock signal delay of each time-to-digital converter node is calibrated to a preset accuracy threshold, and the calibrated optical clock signal is output.

[0009] Inject a standard clock signal into the clock buffer input channel to drive the clock buffer into working state; connect the clock buffer output channel to the input channel of the time-to-digital converter node in the time-to-digital converter array, use the calibrated optical clock signal to trigger the time-to-digital converter array, collect the timestamp data of each output channel of the clock buffer, and generate the original time dataset.

[0010] The original time dataset is input into the dual mixer to calculate the time deviation value of each output channel of the clock buffer and output multi-channel skew parameters and three-dimensional contour plot.

[0011] The material model is called based on the multi-channel skew parameters, and the multi-channel skew parameters are converted into the lifetime index value of each output channel of the clock buffer. The three-dimensional cloud map is then integrated to form a test conclusion report.

[0012] In a preferred embodiment of the multi-channel clock buffer testing method of the present invention, the step of injecting a standard clock signal into the input channel of the clock buffer to drive the clock buffer into the working state is as follows.

[0013] A standard clock signal is injected into the clock buffer input channel through a standard electrical signal generator.

[0014] The internal phase-locked loop circuit of the clock buffer locks the injected standard clock signal and establishes the synchronous clock signal for the output channels of each clock buffer;

[0015] Monitor the waveform of the synchronous clock signal of each clock buffer output channel. When the waveform of the synchronous clock signal is uninterrupted and the periodic stability meets the minimum time requirement of the synchronous clock signal, the clock buffer is determined to have entered a stable working state.

[0016] As a preferred embodiment of the multi-channel clock buffer testing method of the present invention, the step of triggering a time-to-digital converter array using a calibrated optical clock signal to collect timestamp data from each output channel of the clock buffer and generate an original time dataset is as follows.

[0017] The time-to-digital converter array receives the calibrated optical clock signal as a global trigger signal;

[0018] Each time-to-digital converter node receives a global trigger signal through the optical distribution network. At the rising edge trigger moment of the calibrated optical clock signal, the internal time-to-digital converter circuit is started to capture the rising edge moment of the synchronous clock signal from the clock buffer output channel.

[0019] The time-to-digital converter node records the time offset between the rising edge of the synchronous clock signal and the triggering time of the rising edge of the calibrated optical clock signal through a counting mechanism, forming timestamp data.

[0020] The timestamp data is aggregated to generate the original time dataset.

[0021] As a preferred embodiment of the multi-channel clock buffer testing method of the present invention, the step of inputting the original time dataset into a dual mixer and calculating the time deviation value of each output channel of the clock buffer is as follows.

[0022] Load the raw time dataset into the data input interface of the dual mixer;

[0023] The dual mixer processor performs mixing processing on the time offset value of the synchronous clock signal in the original time data set and extracts the time deviation variation characteristics of the same output channel of the clock buffer between consecutive periods.

[0024] Based on the time deviation variation characteristics, the dual mixer processor calculates the time deviation value of each output channel in the clock buffer relative to the global trigger time of the calibrated optical clock signal.

[0025] As a preferred embodiment of the multi-channel clock buffer testing method of the present invention, the multi-channel skew parameter is a data set generated by classifying the time deviation values ​​of all output channels of the clock buffer according to the channel number.

[0026] As a preferred embodiment of the multi-channel clock buffer testing method of the present invention, the three-dimensional cloud map is constructed by a three-dimensional visualization processing component in a three-dimensional coordinate system to build a time deviation distribution model, and the time deviation values ​​in the time deviation distribution model are mapped into a point cloud form of graphic using color gradient.

[0027] As a preferred embodiment of the multi-channel clock buffer testing method of the present invention, the step of calling the material model based on the multi-channel skew parameters to convert the multi-channel skew parameters into lifetime index values ​​for each output channel of the clock buffer is as follows.

[0028] Load multi-channel skew parameters into the data interface of the material model;

[0029] The material model extracts the time deviation value of each output channel of the clock buffer from the multi-channel skew parameters, searches for the material aging state that matches the time deviation value in the preset aging database, and generates a material aging mapping relationship.

[0030] The material model uses a lifetime conversion circuit to compare the lifetime data table in the aging database with the material aging mapping relationship, and generates the lifetime index value for each output channel of the clock buffer.

[0031] Secondly, the present invention provides a multi-channel clock buffer testing system, comprising,

[0032] The calibration module is used to distribute the optical clock signal to the time-to-digital converter array, calibrate the optical clock signal delay of each time-to-digital converter node to a preset accuracy threshold, and output the calibrated optical clock signal.

[0033] The acquisition module is used to inject a standard clock signal into the input channel of the clock buffer to drive the clock buffer into the working state; it connects the output channel of the clock buffer to the input channel of the time-to-digital converter node in the time-to-digital converter array, uses the calibrated optical clock signal to trigger the time-to-digital converter array, acquires the timestamp data of each output channel of the clock buffer, and generates the original time dataset.

[0034] The processing module is used to input the raw time dataset into the dual mixer, calculate the time deviation value of each output channel of the clock buffer, and output multi-channel skew parameters and three-dimensional contour plot.

[0035] The testing module is used to call the material model based on the multi-channel skew parameters, convert the multi-channel skew parameters into the lifetime index value of each output channel of the clock buffer, and integrate the three-dimensional cloud map to form a test conclusion report.

[0036] Thirdly, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, wherein the computer program, when executed by the processor, implements any step of the multi-channel clock buffer testing method as described in the first aspect of the present invention.

[0037] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the multi-channel clock buffer testing method as described in the first aspect of the present invention.

[0038] The beneficial effects of this invention are as follows: By performing two mixing processes on the original time dataset using a dual-mixer processor, and combining phase detection and spectrum analysis, high-precision extraction of the time deviation values ​​of each output channel of the clock buffer is achieved. Two local oscillator signals of different frequencies are used to perform difference-frequency conversion on the time offset values, transforming weak timing fluctuations into analyzable low-frequency signals. Then, the variation pattern of the synchronous clock signal within a continuous period is identified through phase offset and frequency domain characteristics. This not only effectively improves the resolution and stability of time deviation calculation, but also accurately captures subtle skew differences between channels even in complex noise environments. Therefore, it provides a precise data foundation for the generation of multi-channel skew parameters and 3D visualization, enhancing the intuitiveness and engineering practicality of the test results. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a flowchart of a multi-channel clock buffer test method.

[0041] Figure 2 This is a schematic diagram of a multi-channel clock buffer test system.

[0042] Figure 3 This is a flowchart of the dual-mixer process.

[0043] Figure 4 This is a flowchart for converting lifespan indicators. Detailed Implementation

[0044] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0045] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0046] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0047] Reference Figures 1-4 As one embodiment of the present invention, this embodiment provides a multi-channel clock buffer testing method, including the following steps:

[0048] S1. Distribute the optical clock signal to the time-to-digital converter array, calibrate the optical clock signal delay of each time-to-digital converter node to a preset accuracy threshold, and output the calibrated optical clock signal.

[0049] Furthermore, the optical clock signal generated by the femtosecond laser reference source is distributed proportionally to each time-to-digital converter node in the ring-shaped time-to-digital converter array through a star-shaped optical distribution network.

[0050] Single-mode fiber is used to construct all branch paths of the optical distribution network, and the length of each branch path is kept physically symmetrical to initially reduce the optical path difference. Specifically, starting from the output port of the femtosecond laser reference source, single-mode fiber is selected as the transmission medium of the optical distribution network, ensuring that the core diameter and refractive index of each single-mode fiber are consistent to guarantee that the transmission characteristics of the optical clock signal are the same in each branch path. The single-mode fibers are arranged in a star topology and connected from the output port of the femtosecond laser reference source to the central splitter of the optical distribution network. The central splitter has multiple ports with equal power output, each port corresponding to a time-to-digital converter node. Each single-mode fiber is precisely cut using a fiber cleaver to ensure that the distance from the central splitter to each time-to-digital converter node is consistent. The single-mode optical fibers are of equal length, forming a physically symmetrical structure. The length of each single-mode optical fiber is verified by high-precision measurement equipment to ensure that the length deviation is less than a preset fiber length threshold. During connection, the input end of each single-mode optical fiber is fixed to the output port of the central optical splitter, and the output end is connected to the receiving port of the corresponding time-to-digital converter node. Fiber optic couplers are used to ensure that the signal loss at the connection point is minimized. After the connection is completed, the transmission quality of each single-mode optical fiber is detected by an optical time-domain reflectometer to confirm that there are no breaks or abnormal losses, thus forming all branch paths of the optical distribution network. The fiber length threshold is set based on the transmission speed of the optical clock signal in the single-mode optical fiber and the measurement accuracy requirements of the time-to-digital converter node, for example, a value of 0.1 mm to 1 mm.

[0051] The optical path difference between each branch path and the reference path is detected using a high-precision interferometric measurement tool (such as a Michelson interferometer); where the reference path is a branch optical path in the optical distribution network that is selected as the reference for optical path difference measurement.

[0052] The measured optical path difference is fed back to the control center of the miniature electric displacement stage;

[0053] The micro electric displacement stage control center adjusts the installation position of the corresponding fiber end face at the coupler interface in each branch path according to the optical path difference. By changing the relative distance between the fiber end face and the coupler, it achieves precise control of the optical clock signal transmission path length.

[0054] During the adjustment process, the time arrival deviation of the optical clock signal received by each time-to-digital converter node relative to the reference node is continuously monitored; wherein, the reference node is a time-to-digital converter node in the time-to-digital converter array selected as the reference for measuring the time arrival deviation.

[0055] Based on the measurement accuracy requirements of time-to-digital converter nodes in multi-channel clock buffer testing, an accuracy threshold is set. After verifying whether the optical clock signal deviation of each time-to-digital converter node meets the preset accuracy threshold (if the time arrival deviation between all time-to-digital converter nodes is less than 0.1 picoseconds, the calibration is considered complete), the calibrated optical clock signal is output.

[0056] S2. Inject a standard clock signal into the clock buffer input channel to drive the clock buffer into the working state; connect the clock buffer output channel to the input channel of the time-to-digital converter node in the time-to-digital converter array, use the calibrated optical clock signal to trigger the time-to-digital converter array, collect the timestamp data of each output channel of the clock buffer, and generate the original time dataset.

[0057] Furthermore, a standard clock signal generated by a standard electrical signal generator with a reference frequency of 100MHz is connected to the clock buffer input channel. The clock buffer input channel is equipped with a 50-ohm impedance matching circuit to ensure the integrity of the standard clock signal. 100MHz is one of the standard frequencies in many industries such as high-speed digital circuits and test and measurement, and is widely used in various high-speed data transmission and synchronization scenarios. The 50-ohm impedance matching circuit is a standard characteristic impedance in many industries such as high-speed digital circuits and RF / test and measurement. Using a 50-ohm impedance matching circuit can effectively reduce the reflection of the standard clock signal and ensure that the standard clock signal injected into the clock buffer has good integrity.

[0058] After the standard clock signal is input, the phase-locked loop circuit inside the clock buffer begins to lock the input standard clock signal and gradually establishes the synchronous clock signal of each output channel of the clock buffer.

[0059] When all output channels of the clock buffer detect a valid standard clock signal output and meet the minimum time requirement of the synchronization clock signal, the clock buffer is determined to have entered a stable operating state. Specifically, the signal detection circuit of each output channel of the clock buffer continuously monitors the synchronization clock signal output from the internal phase-locked loop circuit, confirming that each output channel generates a synchronization clock signal waveform with the same frequency as the input standard clock signal, and that the clock signal waveform is uninterrupted or distorted. The signal detection circuit verifies that the periodic stability of the synchronization clock signal reaches the preset minimum time requirement of the synchronization clock signal by comparing the rising and falling edges of the synchronization clock signal (based on the periodic stability of a 100MHz standard clock signal). The clock signal period is defined (e.g., a minimum time requirement of 10 nanoseconds), meaning the clock signal period is continuous and without significant jitter. The clock signal detection circuit for each output channel is used, and the detection results are fed back to the clock buffer status register. The clock buffer status register records the clock signal status of all output channels. When the clock buffer status register confirms that all output channels continuously output a stable clock signal waveform, and the clock signal waveform period conforms to the frequency characteristics of a 100MHz standard clock signal (e.g., a clock signal waveform period of 10 nanoseconds with no abnormal fluctuations), it is determined that the clock buffer has entered a stable working state, providing a reliable synchronous clock signal for subsequent connection of time-to-digital converter nodes.

[0060] Each output channel of the clock buffer is connected to the input channel of the corresponding time-to-digital converter node in the time-to-digital converter array via a high-frequency coaxial cable.

[0061] The time-to-digital converter array receives the calibrated optical clock signal as a global trigger signal;

[0062] Each time-to-digital converter (TDD) node receives a global trigger signal through the optical distribution network. At the rising edge trigger time of the calibrated optical clock signal, each TDD node begins high-precision time measurement of the synchronization clock signal from the clock buffer output channel. Specifically, after receiving the rising edge trigger time of the calibrated optical clock signal, each TDD node activates its internal time-to-digital converter circuit to accurately capture the rising edge time of the synchronization clock signal from the clock buffer output channel. Using a preset time resolution of 0.5 picoseconds, the TDD node records the time of the synchronization clock signal's rising edge relative to the calibrated optical clock signal's rising edge trigger time through the counting mechanism of the time-to-digital converter circuit. Time offset value; each time-to-digital converter (TDD) node ensures that the capture process is synchronized with the global trigger signal to guarantee that the measurement time base of all TDD nodes is consistent; the rising edge of the captured synchronization clock signal is converted into digital timestamp data by the TDD node and stored in the internal register of the TDD node; the entire measurement process is controlled by the high-speed clock of the TDD node to ensure that the accuracy of the timestamp data reaches the 0.5 picosecond resolution requirement, thereby completing the high-precision time measurement of the synchronization clock signal; among which, 0.5 picosecond resolution is the standard value of TDD in high-precision clock testing, which is commonly used in applications that meet the requirements of sub-picosecond timing measurement, such as multi-channel clock buffer testing;

[0063] Each time-to-digital converter node records the time offset value between the rising edge of the synchronization clock signal and the triggering time of the rising edge of the calibrated optical clock signal through a counting mechanism, forming timestamp data;

[0064] The timestamp data recorded by all time-to-digital converter nodes are aggregated to generate the original time dataset.

[0065] It should be noted that the initial distribution and calibration of the optical clock signal is to ensure that the time-to-digital converter node receives a high-precision synchronization signal. This step uses the calibrated optical clock signal to trigger the time-to-digital converter array in order to ensure the timing consistency of timestamp data acquisition.

[0066] S3. Input the original time dataset into the dual mixer, calculate the time deviation value of each output channel of the clock buffer, and output the multi-channel skew parameters and three-dimensional contour plot.

[0067] Furthermore, the raw time dataset is loaded into the data input interface of the dual mixer;

[0068] The dual mixer processor performs mixing on the time offset value of the synchronous clock signal in the original time dataset, and extracts the time deviation variation characteristics of the same output channel of the clock buffer between consecutive periods; specifically as follows:

[0069] The dual-frequency mixer receives the raw time dataset from the data input interface and extracts the time offset value of the synchronous clock signal of each clock buffer output channel recorded in the raw time dataset. The dual-frequency mixer is internally configured with two local oscillator signal generators with a frequency difference of 10MHz to generate the first local oscillator signal and the second local oscillator signal, respectively.

[0070] The dual-mixer processor performs a first mixing process on the time offset value of the synchronous clock signal output channel of each clock buffer and the first local oscillator signal to generate a first beat signal. Specifically, the first mixing process involves: loading the time offset value of the synchronous clock signal onto the input of the internal mixing circuit of the dual-mixer processor; the internal mixing circuit receives the first local oscillator signal generated by the local oscillator signal generator of the dual-mixer processor, which has a fixed frequency, for example, 100MHz; the internal mixing circuit includes a nonlinear mixer that receives the time offset value of the synchronous clock signal extracted from the original time dataset and the first local oscillator signal generated by the local oscillator signal generator of the dual-mixer processor; the nonlinear mixer, through its nonlinear mixing characteristics, mixes the digital signal corresponding to the time offset value of the synchronous clock signal with the analog waveform of the first local oscillator signal to generate a mixed signal; the multiplication circuit inside the nonlinear mixer performs a multiplication on the digital signal corresponding to the time offset value of the synchronous clock signal and the instantaneous value of the first local oscillator signal. The process involves point-by-point conversion, transforming the mixed signal into a first intermediate signal. A nonlinear mixer shapes this first intermediate signal using its internal signal conditioning circuit, retaining the low-frequency component dominated by the difference between the synchronous clock signal's time offset frequency and the first local oscillator frequency, forming the pre-filter intermediate signal. A bandpass filter in the dual-mixer's internal mixing circuit receives this pre-filter intermediate signal. The bandpass filter's center frequency (e.g., 10MHz) is aligned with the low-frequency component of the difference between the synchronous clock signal's time offset frequency and the first local oscillator frequency. Through its bandpass frequency selection characteristics, the bandpass filter allows low-frequency components in the pre-filter intermediate signal that match the difference between the synchronous clock signal's time offset frequency and the first local oscillator frequency to pass through, while simultaneously blocking high-frequency noise and irrelevant frequency components. The processed low-frequency components are output as the first beat signal and stored in the dual-mixer's internal buffer. The bandpass filter's processing of the pre-filter first intermediate signal is achieved through a capacitor and inductor network of an analog circuit, ensuring that the output signal retains only the low-frequency components.

[0071] Next, the first beat signal and the second local oscillator signal are mixed a second time to generate the second beat signal. Specifically, the second mixing process involves: the mixing circuit inside the dual mixer extracting the first beat signal from its internal buffer and loading it onto the input of the nonlinear mixer; the nonlinear mixer receiving the second local oscillator signal generated by the dual mixer's local oscillator signal generator, which has a fixed frequency, for example, 90MHz; the nonlinear mixer using its nonlinear mixing characteristics mixing the low-frequency component of the first beat signal with the analog waveform of the second local oscillator signal to generate a mixed signal; the multiplication circuit inside the nonlinear mixer performing point-by-point conversion on the instantaneous values ​​of the first beat signal and the second local oscillator signal, converting the mixed signal into a second intermediate signal; and the nonlinear mixer shaping the second intermediate signal using its internal signal conditioning circuit, retaining the low-frequency component dominated by the difference between the frequencies of the first beat signal and the second local oscillator signal, thus forming the second beat signal, which is stored in the internal buffer of the dual mixer.

[0072] The dual mixer analyzes the phase characteristics of the second beat signal through a phase detection circuit to identify the variation pattern of the synchronization clock signal time offset value in continuous periods of the same output channel of the clock buffer. Specifically, the dual mixer extracts the second beat signal from its internal register and loads it onto the input of the phase detection circuit. The phase detection circuit includes a phase comparator that receives the second beat signal and compares it with the internal reference clock signal of the dual mixer. The phase comparator detects the rising edge of the second beat signal cycle by cycle, capturing the phase offset of the second beat signal relative to the reference clock signal. The sampling component of the phase detection circuit records the phase offset value of the second beat signal in multiple continuous periods at fixed time intervals, for example, 1 nanosecond, forming a phase offset sequence. The analysis component of the phase detection circuit receives the phase offset sequence and performs point-by-point analysis through its internal digital processing circuit. The process involves: examining the phase offset values ​​in the phase offset sequence and recording their fluctuations within consecutive periods; loading the phase offset sequence into the input buffer of the Fast Fourier Transform (FFT) processing component; performing spectral analysis on the phase offset sequence, converting the time-domain data of the phase offset values ​​point by point into frequency-domain data, and generating a spectrum containing the frequency components of the phase offset; analyzing the spectrum to detect periodically occurring peaks in the frequency-domain data, which correspond to recurring phase offset patterns in the phase offset sequence; associating the detected peak patterns with the time offset value of the synchronization clock signal of the clock buffer output channel to identify recurring phase offset patterns in the phase offset sequence and determine the variation pattern of the synchronization clock signal time offset value of the same output channel of the clock buffer within consecutive periods.

[0073] The phase detection circuit converts the change pattern into a time deviation change characteristic, which is stored in the internal register of the dual mixer.

[0074] Based on the time deviation variation characteristics, the dual mixer calculates the time deviation value of each output channel in the clock buffer relative to the global trigger time of the calibrated optical clock signal, expressed as:

[0075]

[0076] Among them, T v The time deviation value represents the time offset (in seconds) of the synchronous clock signal of the clock buffer output channel relative to the global trigger time of the calibrated optical clock signal. o The phase offset value is extracted from the phase offset sequence of the second beat signal by the phase detection circuit, reflecting the periodic change law of the time offset value of the synchronous clock signal (unit: radians). f is the difference between the frequency of the first beat signal and the frequency of the second local oscillator signal (unit: Hertz), which is determined by the dual mixer when generating the second beat signal. π is pi, a mathematical constant, approximately equal to 3.14159, used to provide the conversion basis between angle and period when converting the phase offset value into a time deviation value.

[0077] The time deviation values ​​of all output channels of the clock buffer are categorized by channel number to generate multi-channel skew parameters;

[0078] Using the channel number information and corresponding time deviation values ​​from the multi-channel skew parameters, a time deviation distribution model is constructed in a three-dimensional coordinate system, and the time deviation values ​​are mapped to a three-dimensional cloud map using a color gradient. Specifically, the channel number information and corresponding time deviation value of each output channel of the clock buffer are extracted from the multi-channel skew parameters. The channel number information represents the physical location identifier of the clock buffer output channel, and the time deviation value represents the timing offset of the clock buffer output channel relative to the global trigger time of the calibrated optical clock signal. A three-dimensional coordinate system is established using a three-dimensional visualization processing component, where the X and Y axes represent the physical spatial distribution of the clock buffer output channels, and the Z axis represents the magnitude of the time deviation value. The channel number information is mapped to the X and Y axes of the three-dimensional coordinate system to form the clock buffer output channel... Spatial location points; each spatial location point is associated with a corresponding time deviation value, mapped to the Z-axis height, forming a time deviation distribution model; the time deviation distribution model converts the magnitude of the time deviation value into a color value through color gradient mapping, for example, the color gradient gradually changes from blue (representing a smaller time deviation value) to red (representing a larger time deviation value); the 3D visualization processing component renders the time deviation distribution model into a 3D cloud map based on the color gradient mapping; for example, smaller time deviation values ​​are mapped to blue, and larger time deviation values ​​are mapped to red, forming a color value dataset; the rendering engine draws each spatial location point in point cloud form, assigns a corresponding color to each point using the color value dataset, and generates a point cloud graphic; the rendering engine optimizes the lighting and shadow effects of the point cloud graphic to enhance the three-dimensionality of the spatial location points, forming a 3D cloud map;

[0079] The 3D cloud map presents the spatial temporal deviation distribution information of different clock buffer output channels in the form of a visualized point cloud (such as a point cloud). The output results include multi-channel skew parameters and 3D cloud map.

[0080] S4. Based on the multi-channel skew parameters, call the material model, convert the multi-channel skew parameters into the lifetime index value of each output channel of the clock buffer, and integrate the three-dimensional cloud map to form a test conclusion report.

[0081] Furthermore, multi-channel skew parameters are loaded as input data into the data interface of the material model;

[0082] The material model, based on the time deviation value of each output channel of the clock buffer in the multi-channel skew parameters, searches for the material aging state corresponding to the time deviation value in a pre-set aging database and matches the corresponding material aging mapping relationship. Specifically, the material model extracts the time deviation value of each output channel of the clock buffer from the multi-channel skew parameters; the time deviation value represents the timing offset of the clock buffer output channel relative to the global trigger time of the calibrated optical clock signal. The material model accesses the pre-set aging database through a data interface; the aging database stores the aging characteristic data of the clock buffer material under different time deviation values. The material model compares the time deviation value of each clock buffer output channel with the time deviation value entries in the aging database one by one, searches for the aging characteristic data entry that matches the time deviation value, and determines the corresponding material aging state. The aging state reflects the degree of performance degradation of the clock buffer output channel material; for example, the aging state may be slight degradation or severe degradation. Based on the search results, the material model extracts a mapping table from the aging database that associates the aging state with the material, generating a material aging mapping relationship. This mapping relationship corresponds the time deviation value to the material aging state. The material aging mapping relationship is stored in an internal buffer of the material model. The aging database is an existing database, commonly used in clock buffer testing and semiconductor reliability analysis, used to store aging characteristic data of materials under different time deviation values ​​or operating conditions, such as performance degradation records accumulated based on experiments or historical tests. The material model is an existing model, commonly used in semiconductor reliability testing, used to match the time deviation value of the clock buffer with the material aging state in the aging database to generate a lifetime index value.

[0083] The lifetime index value of each output channel of the clock buffer is output based on the matched material aging mapping relationship. Specifically: the material model extracts the material aging mapping relationship from the internal buffer; the material model accesses the lifetime data table associated with the material aging state in the preset aging database through the lifetime conversion circuit. The lifetime data table stores the remaining lifetime information of the clock buffer material under different aging states; the lifetime conversion circuit compares each time deviation value in the material aging mapping relationship with the entry in the lifetime data table to find the remaining lifetime value corresponding to the material aging state; the remaining lifetime value represents the expected operating time of the clock buffer output channel under the current time deviation value, for example, the remaining lifetime value is 1000 hours to 10000 hours; the lifetime conversion circuit generates a lifetime index value for each output channel of the clock buffer according to the comparison result. The lifetime index value reflects the long-term timing stability of the output channel.

[0084] By comparing the life index value with the preset health management threshold, when the life index value is lower than the health management threshold, a fault warning message is generated to indicate the timing instability risk of the clock buffer output channel (such as excessive jitter of the synchronization clock signal, abnormal period fluctuation, or excessive time deviation between clock buffer output channels); the health management threshold is set based on the remaining life information in the clock buffer material aging database and the test accuracy requirements, for example, a value of 1000 hours.

[0085] The lifetime index values ​​of all output channels of the clock buffer are categorized by channel number to generate a lifetime index parameter list.

[0086] The life index parameter list and the time deviation distribution information in the 3D cloud map are spatially superimposed in a unified coordinate system;

[0087] The visualization interface synchronously displays a 3D cloud map with lifespan index annotations and time deviation distribution information.

[0088] A test conclusion report is generated based on a list of lifespan index parameters and a 3D cloud map.

[0089] This embodiment also provides a multi-channel clock buffer testing system, including:

[0090] The calibration module is used to distribute the optical clock signal to the time-to-digital converter array, calibrate the optical clock signal delay of each time-to-digital converter node to a preset accuracy threshold, and output the calibrated optical clock signal.

[0091] The acquisition module is used to inject a standard clock signal into the input channel of the clock buffer to drive the clock buffer into the working state; it connects the output channel of the clock buffer to the input channel of the time-to-digital converter node in the time-to-digital converter array, uses the calibrated optical clock signal to trigger the time-to-digital converter array, acquires the timestamp data of each output channel of the clock buffer, and generates the original time dataset.

[0092] The processing module is used to input the raw time dataset into the dual mixer, calculate the time deviation value of each output channel of the clock buffer, and output multi-channel skew parameters and three-dimensional contour plot.

[0093] The testing module is used to call the material model based on the multi-channel skew parameters, convert the multi-channel skew parameters into the lifetime index value of each output channel of the clock buffer, and integrate the three-dimensional cloud map to form a test conclusion report.

[0094] This embodiment also provides a computer device applicable to the multi-channel clock buffer testing method, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the multi-channel clock buffer testing method proposed in the above embodiment.

[0095] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0096] This embodiment also provides a storage medium storing a computer program, which, when executed by a processor, implements the multi-channel clock buffer testing method proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0097] In summary, this invention achieves high-precision extraction of time deviation values ​​for each output channel of the clock buffer by performing two mixing processes on the original time dataset using a dual-mixer processor, combined with phase detection and spectral analysis. By utilizing two local oscillator signals of different frequencies to perform difference-frequency conversion on the time offset values, subtle timing fluctuations are transformed into analyzable low-frequency signals. Furthermore, the variation patterns of the synchronous clock signal within continuous periods are identified through phase offset and frequency domain characteristics. This not only effectively improves the resolution and stability of time deviation calculation but also accurately captures subtle skew differences between channels even in complex noise environments. Therefore, it provides a precise data foundation for the generation of multi-channel skew parameters and 3D visualization, enhancing the intuitiveness and engineering applicability of the test results.

[0098] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A test method for a multi-channel clock buffer, characterized in that: include, The optical clock signal is distributed to the time-to-digital converter array, the optical clock signal delay of each time-to-digital converter node is calibrated to a preset accuracy threshold, and the calibrated optical clock signal is output. Inject a standard clock signal into the clock buffer input channel to drive the clock buffer into the working state; Connect the clock buffer output channel to the input channel of the time-to-digital converter node in the time-to-digital converter array, trigger the time-to-digital converter array with the calibrated optical clock signal, collect the timestamp data of each output channel of the clock buffer, and generate the original time dataset. The original time dataset is input into the dual mixer to calculate the time deviation value of each output channel of the clock buffer and output multi-channel skew parameters and three-dimensional contour plot. The material model is called based on the multi-channel skew parameters, and the multi-channel skew parameters are converted into the lifetime index value of each output channel of the clock buffer. The three-dimensional cloud map is then integrated to form a test conclusion report.

2. The multi-channel clock buffer test method as described in claim 1, characterized in that: The process of injecting a standard clock signal into the clock buffer's input channel to drive the clock buffer into its working state is as follows: A standard clock signal is injected into the clock buffer input channel through a standard electrical signal generator. The internal phase-locked loop circuit of the clock buffer locks the injected standard clock signal and establishes the synchronous clock signal for the output channels of each clock buffer; Monitor the waveform of the synchronous clock signal of each clock buffer output channel. When the waveform of the synchronous clock signal is uninterrupted and the periodic stability meets the minimum time requirement of the synchronous clock signal, the clock buffer is determined to have entered a stable working state.

3. The multi-channel clock buffer test method as described in claim 1, characterized in that: The process involves using a calibrated optical clock signal to trigger a time-to-digital converter array, acquiring timestamp data from each output channel of the clock buffer, and generating a raw time dataset, as detailed below. The time-to-digital converter array receives the calibrated optical clock signal as a global trigger signal; Each time-to-digital converter node receives a global trigger signal through the optical distribution network. At the rising edge trigger moment of the calibrated optical clock signal, the internal time-to-digital converter circuit is started to capture the rising edge moment of the synchronous clock signal from the clock buffer output channel. The time-to-digital converter node records the time offset between the rising edge of the synchronous clock signal and the triggering time of the rising edge of the calibrated optical clock signal through a counting mechanism, forming timestamp data. The timestamp data is aggregated to generate the original time dataset.

4. The multi-channel clock buffer test method as described in claim 1, characterized in that: The process of inputting the original time dataset into the dual mixer and calculating the time deviation value of each output channel of the clock buffer is as follows. Load the raw time dataset into the data input interface of the dual mixer; The dual mixer processor performs mixing processing on the time offset value of the synchronous clock signal in the original time data set and extracts the time deviation variation characteristics of the same output channel of the clock buffer between consecutive periods. Based on the time deviation variation characteristics, the dual mixer processor calculates the time deviation value of each output channel in the clock buffer relative to the global trigger time of the calibrated optical clock signal.

5. The multi-channel clock buffer test method as described in claim 1, characterized in that: The multi-channel skew parameter is a data set generated by classifying the time deviation values ​​of all output channels of the clock buffer according to the channel number.

6. The multi-channel clock buffer test method as described in claim 1, characterized in that: The three-dimensional cloud map is constructed by a three-dimensional visualization processing component in a three-dimensional coordinate system to create a time deviation distribution model, and then the time deviation values ​​in the time deviation distribution model are mapped into a point cloud form using color gradients.

7. The multi-channel clock buffer test method as described in claim 1, characterized in that: The process of calling the material model based on multi-channel skew parameters converts the multi-channel skew parameters into lifetime index values ​​for each output channel of the clock buffer, as detailed below. Load multi-channel skew parameters into the data interface of the material model; The material model extracts the time deviation value of each output channel of the clock buffer from the multi-channel skew parameters, searches for the material aging state that matches the time deviation value in the preset aging database, and generates a material aging mapping relationship. The material model uses a lifetime conversion circuit to compare the lifetime data table in the aging database with the material aging mapping relationship, and generates the lifetime index value for each output channel of the clock buffer.

8. A multi-channel clock buffer test system, based on the multi-channel clock buffer test method according to any one of claims 1 to 7, characterized in that: include, The calibration module is used to distribute the optical clock signal to the time-to-digital converter array, calibrate the optical clock signal delay of each time-to-digital converter node to a preset accuracy threshold, and output the calibrated optical clock signal. The acquisition module is used to inject a standard clock signal into the clock buffer input channel to drive the clock buffer into the working state; Connect the clock buffer output channel to the input channel of the time-to-digital converter node in the time-to-digital converter array, trigger the time-to-digital converter array with the calibrated optical clock signal, collect the timestamp data of each output channel of the clock buffer, and generate the original time dataset. The processing module is used to input the raw time dataset into the dual mixer, calculate the time deviation value of each output channel of the clock buffer, and output multi-channel skew parameters and three-dimensional contour plot. The testing module is used to call the material model based on the multi-channel skew parameters, convert the multi-channel skew parameters into the lifetime index value of each output channel of the clock buffer, and integrate the three-dimensional cloud map to form a test conclusion report.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the multi-channel clock buffer testing method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the multi-channel clock buffer test method according to any one of claims 1 to 7.

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