Multi-channel time-interleaved analog-digital converter

Abstract

The invention provides a multi-channel time-interleaved analog-digital converter. The multi-channel time-interleaved analog-digital converter is characterized in that a clock generation circuit generates a work clock for the converter; an ADC channel set including M ADC channels is configured into a time-interleaved structure; the ADC channels operate in turns in a time division multiplexing under control of the clock generation circuit, a high-speed analog input signal is converted into M low-speed digital output signals, and M is an integer not smaller than 2; a channel mismatch detection circuit detects timing sequence mismatch errors of signals output by the M ADC channel, in real time, so that a timing sequence mismatch parameter of each ADC channel relative to a reference ADC channel is acquired; a signal compensation and reconstruction circuit compensates and reconstructs the digital output signals output by the ADC channel set according to the timing sequence mismatch errors that the channel mismatch detection circuit detects; a signal combiner circuit combines the M low-speed output signals subjected to channel compensation and generated by the signal compensation and reconstruction circuit, and finally a high-speed digital output signal is obtained.

Description

technical field [0001] The invention relates to the field of electronics, in particular to a multi-channel time-interleaved analog-to-digital converter. Background technique [0002] Multi-channel Time-interleaved Analog-to-Digital Converter (Multi-channel Time-interleaved Analog-to-Digital Converter) is a parallel connection of multiple Analog-to-Digital Converters (ADCs), and uses an interleaved clock to make it timed The high-speed ADC architecture that works alternately in division multiplexing can combine the low-speed signals output by each ADC that maintains low-frequency operation into high-speed signals. Ideally, when the ADC circuit parameters of each channel are exactly the same, the sampling rate of the Time-interleaved ADC increases proportionally to the number of interleaved parallel ADC channels. In fact, it is difficult for ADCs of different channels to completely match the sampling time, resulting in a timing mismatch error (timing skew error). If it is no...

AI Technical Summary

Problems solved by technology

In fact, it is difficult for ADCs between different channels to completely match the sampling time, resulting in a timing mismatch error (timing skew error)

If not corrected, it will seriously affect the dynamic performance of Time-interleavedADC

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