Multi-Channel Time-Interleaved Analog-to-Digital Converter

Abstract

The invention provides a multi-channel time interleaving analog-to-digital converter, which includes: a clock generation circuit generates a working clock of the analog-to-digital converter; a channel ADC group includes M ADC channels, which are configured as a time interleaving structure, and the clock generation circuit Under the control, it works in turn according to the time-division multiplexing method, and converts one high-speed analog input signal into M low-speed digital output signals, where M is an integer not less than 2; the channel mismatch detection circuit has a mismatch in the timing of the output signals of the M ADC channels. The matching error is detected in real time, and the timing mismatch parameters of each ADC channel relative to the reference ADC channel are obtained; the signal compensation and reconstruction circuit is based on the timing mismatch error detected by the channel mismatch detection circuit. The digital output signal output by the channel ADC group Compensation and reconstruction are performed; the signal combination circuit combines the M channels of low-speed output signals after compensation of each channel generated by the signal compensation and reconstruction circuit to obtain the final channel of high-speed digital output signals.

Description

technical field [0001] The invention relates to the field of electronics, in particular to a multi-channel time-interleaved analog-to-digital converter. Background technique [0002] Multi-channel Time-interleaved Analog-to-Digital Converter (Multi-channel Time-interleaved Analog-to-Digital Converter) is a kind of parallel connection of multiple Analog-to-Digital Converters (Analog-to-Digital Converter, ADC), and uses interleaved clock to make Its high-speed ADC architecture that rotates in time-division multiplexing can combine the low-speed signals output by each ADC that maintains low-frequency operation into high-speed signals. Ideally, when the ADC circuit parameters of each channel are exactly the same, the sampling rate of the Time-interleaved ADC increases proportionally to the number of interleaved parallel ADC channels. In fact, it is difficult for ADCs of different channels to completely match the sampling time, resulting in a timing mismatch error (timing skewer...

AI Technical Summary

Problems solved by technology

In fact, it is difficult for ADCs between different channels to completely match the sampling time, resulting in a timing mismatch error (timing skewerror)

If not corrected, it will seriously affect the dynamic performance of Time-interleaved ADC

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