Storage unit of novel low-power-consumption static random access memory and application thereof

Abstract

The invention provides a storage unit of a novel low-power-consumption static random access memory, which is characterized by comprising five word lines and four bit lines, the five word lines are respectively a word line I, a word line II, a word line III, a word line IV and a word line 5, and the four bit lines are respectively a bit line I, a bit line II, a bit line III and a bit line IV. Compared with the most advanced technology, energy consumption is reduced to 24.5% of original energy consumption, and the method has the advantages that the characteristic that cmos channel current and grid voltage are positively correlated is utilized, and a set of analog voltage values serve as the result of driving a SRAM through the grid voltage, so that in the same starting time, the voltage analog value on the bit line represents the multiplication result.

Description

technical field [0001] The invention relates to a storage unit of a new low-power consumption static random access memory based on two bits by two bits of input data, and also relates to an application structure of the above-mentioned new SRAM storage unit. Background technique [0002] The in-memory computing unit based on input data is a storage unit of a new type of static random access memory that realizes in-memory computing multi-bit multiplication. In traditional computer architectures, operations on data require multiple clock cycles and require significant additional power consumption. The method of in-memory calculation makes the storage unit have the function of calculation at the same time, and the calculation result is directly read out during the reading process. In the mode of in-memory operation, there is a trade-off between output accuracy and energy consumption. The reading speed of in-memory computing should be close to that of traditional corresponding ...

AI Technical Summary

Problems solved by technology

[0013] The disadvantage of the digital method is that it requires more than one clock cycle, for example, a four-bit addition operation requires four clock cycles, and a two-bit multiplication requires seven clock cycles

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