53 results about "Resistive type" patented technology

The invention belongs to insulation of superconducting power equipment, and particularly relates to a breakdown voltage prediction method for a liquid nitrogen, insulation barrier and bubble composite system. Comprising the following steps: acquiring electric field distribution characteristic parameters of the resistance type superconducting current limiter through simulation, and designing an equivalent electrode structure capable of reproducing electric field characteristics in a liquid nitrogen environment; establishing a first breakdown voltage prediction model taking the insulation barrier position parameters and the electrode spacing as variables; calculating the surface heat flux of the superconducting strip in the quench fault state; and introducing a bubble influence factor for correction to obtain a second breakdown voltage prediction model. A complex actual insulation system prediction problem is converted into an equivalent model problem which can be verified in a laboratory. And an accurate basis is provided for the insulation design of the resistance-type superconducting current limiter.

An endoscopic medical instrument comprises a host and an assembly, the assembly is detachably mounted on the host, the host comprises an identification circuit, the assembly comprises an identity confirmation structure, and the identity confirmation structure comprises the following three types: a resistance type, a chip type or a resistance chip type; and the identification circuit can identify the resistance values of the chip and the identification resistor so as to judge the type of the identity confirmation mechanism. The endoscope medical instrument can be compatible with different types of components, the types of the components can be quickly identified, corresponding programs can be executed, and the working efficiency of doctors can be improved.

The invention provides a resistance type whisker sensor, an electronic skin and a preparation method thereof, the resistance type whisker sensor comprises a substrate layer, a liquid metal-carbon nanotube sensitive material layer and a packaging layer, the liquid metal-carbon nanotube sensitive material layer is packaged between the substrate layer and the packaging layer, the liquid metal-carbon nano tube sensitive material forms a conductive network, the conductive network is composed of liquid metal particles and carbon nano tubes generated by laser ablation, and the liquid metal particles are connected through the carbon nano tubes. In the nature, many organisms realize high-precision tactile detection by virtue of tentacles, for example, beards of animals such as cats and rats can sense tiny changes of the surrounding environment and recognize the shape, texture and vibration information of objects, and the high-sensitivity tactile sensing capability plays an important role in survival and environmental adaptation of the animals. The invention provides the high-sensitivity electronic whisker, and provides the electronic skin based on the whisker sensor array.

The invention discloses a resistance-type high-temperature superconducting current limiter simulation model building method, which is used for carrying out analogue simulation on a resistance-type superconducting current limiter made of YBCO (Yttrium Barium Copper Oxide) superconducting tape, and comprises the following steps: S1, building an electrical model module of the resistance-type superconducting current limiter; s2, building a thermodynamic model module of the resistance type superconducting current limiter; s3, carrying out iterative circulation on the electrical model module and the thermodynamic model module; and S4, packaging the electrical model module, the thermodynamic model module and the oscilloscope reading module to obtain a resistance-type superconducting current limiter simulation model so as to access a power grid model. According to the invention, analogue simulation of the resistance-type high-temperature superconducting current limiter can be realized, and the resistance-type high-temperature superconducting current limiter can be connected into a simulation power grid for testing.

The invention discloses an optimal configuration method for a resistance-type superconducting current limiter in a distributed power supply access scene. The method comprises the following steps: S1, carrying out site selection on a resistance-type superconducting current limiter mounting branch; s2, establishing a target function F1 by taking the lowest cost of the resistance type superconducting current limiter as a target; s3, establishing a target function F2 by taking the optimal matching degree of the resistance type superconducting current limiter and current protection as a target; s4, normalizing the objective functions of the F1 and the F2, and constructing a single objective function; s5, establishing constraint conditions of the optimization configuration model of the resistance type superconducting current limiter; and S6, solving the configuration model to obtain an optimal configuration scheme. According to the method, the possible access positions of the RSFCL are screened through sensitivity analysis, then the length, the installation positions and the installation number of the superconducting tape of the RSFCL are taken as decision variables, the cost of the current limiter and the cooperation degree with protection are comprehensively considered, a 10kV distribution network optimal configuration model of the RSFCL in a DG access scene is established, and an optimal configuration scheme of the RSFCL is obtained through solving.

The invention discloses an input load compensation circuit, a digital-to-analog converter and a method for an R-2R resistive DAC (Digital-to-Analog Converter), and aims to solve the problem of unstable reference voltage caused by the change of an input load along with an input code. The circuit comprises a trend compensation branch and an adjacent code compensation branch which are both connected between a first reference voltage and a second reference voltage. The trend compensation branch controls a first resistance network through a thermometer decoder and generates a first compensation current used for compensating the overall change trend of the current. And the adjacent code compensation branch controls the second resistance network through the XOR gate circuit to generate a second compensation current for compensating the current difference between adjacent code words. Through a dual compensation mechanism, the total current on the reference voltage is effectively stabilized, and the linearity and the dynamic performance of the DAC are remarkably improved.

Provided is a product sum calculator which consumes little energy and has high calculation accuracy. A product sum arithmetic unit (1) is configured from: a resistive digital-to-analog conversion unit (11) that is provided with a plurality of RDACs and that converts digital values of each element of an input vector into analog voltages and outputs the analog voltages; a capacitive digital-to-analog conversion unit (12), which is provided with a plurality of CDACs, to which the analog voltage output from the resistive digital-to-analog conversion unit (11) is inputted, and which sets a capacitance ratio corresponding to the digital value of each element of the matrix between input and output terminals and between the output terminal and ground; a successive approximation-type analog-to-digital conversion unit (13) provided with a plurality of successive approximation-type ADCs for converting the voltage of a node commonly connected to each output terminal of the capacitive digital-to-analog conversion unit (12) into a digital value and outputting the digital value; and a consumption current control unit (14) for controlling the consumption current of the resistive digital-to-analog conversion unit (11), the output from the successive comparison analog-to-digital conversion unit (13) being an output vector.

The invention discloses an optimal configuration method for a resistance type superconducting current limiter in a closed-loop transfer scene. The method comprises the following steps: S1, simplifying and setting relay protection in a 10kv cable network; s2, calculating an impact current caused by loop closing transfer; s3, determining the access position of the resistance-type superconducting current limiter in the closed-loop transfer scene; s4, establishing a target function F1 by taking the lowest cost of the resistance type superconducting current limiter as a target; s5, establishing a target function F2 by taking the optimal matching degree of the resistance type superconducting current limiter and current protection as a target; s6, normalizing the objective functions of the F1 and the F2, and constructing a single objective function; s7, establishing constraint conditions of the optimization configuration model of the resistance type superconducting current limiter; and S8, solving the optimization configuration model of the resistance type superconducting current limiter to obtain an optimization configuration scheme of the resistance type superconducting current limiter. According to the method, the optimal configuration of the SFCL in the 10kV distribution network in the closed-loop transfer scene can be realized, and the current limiting ratio at the closed-loop point reaches a relatively high value, so that the reliable action of protection is ensured.

A memory array includes hybrid memory cells, wherein each hybrid memory cell includes a transistor-type memory including a memory film extending on a gate electrode; a channel layer extending on the memory film; a first source / drain electrode extending on the channel layer; and a second source / drain electrode extending along the channel layer; and a resistive-type memory including a resistive memory layer, wherein the resistive memory layer extends between the second source / drain electrode and the channel layer.

The utility model discloses a kind of high-efficiency heat dissipation resistance bimetallic strip, it is related to bimetallic strip technical field, including upper metal sheet, the bottom of the upper metal sheet is equipped with lower metal sheet, and the inside of the upper metal sheet and lower metal sheet is equipped with inner metal sheet, the side of the upper metal sheet is equipped with connecting plate, the inside of the connecting plate is fixedly connected with connecting column, the inside of the connecting column is threadedly connected with fixed bolt one, the side of the inner metal sheet is fixedly connected with heat-conducting sheet, the utility model is equipped with inner metal sheet inside the upper metal sheet and lower metal sheet, inner metal sheet inside fixedly connected heat-conducting sheet can absorb the heat on inner metal sheet, upper metal sheet and lower metal sheet inside the arc-shaped groove inside and heat-conducting sheet are clamped, the copper sheet of arc-shaped groove inside is in contact with heat-conducting sheet, heat is quickly discharged by radiating bump one and radiating bump two, improve the heat dissipation of resistance bimetallic strip.

This invention discloses a resistance testing method, relating to the technical field of intelligent testing, comprising the following steps: Step S100, testing a resistor of any type, independently analyzing the test results to obtain its own characteristics; Step S200, performing forward and reverse tests on the resistor under test according to the testing method, obtaining positive and negative results; Step S300, classifying the resistor under test into grades based on the positive and negative results and its own characteristics. This invention improves the scientific nature of subsequent analysis and the rationality of test parameters by screening effective historical data, avoiding irreversible damage to the resistor, and improving the economy of testing. By taking the average value of forward and reverse tests and analyzing the difference, it eliminates unidirectional systematic errors such as contact resistance, lead resistance, and thermoelectric potential.

The application discloses a resistance type airflow sensor, comprising: a front shell; a rear shell clamped at the rear end of the front shell; and a sensing element packaged between the front shell and the rear shell, wherein the sensing element comprises a hard plate base material and a sensing chip, the hard plate base material is fixedly installed with the front shell, the sensing chip is fixedly installed with the rear shell, one side of the hard plate base material is provided with a sensitive membrane, and the sensing chip is connected with the sensitive membrane through a wire harness. The protective plate is arranged on the front shell and the rear shell, the fan-shaped rubber pieces on the inner wall of the protective plate are mutually adsorbed and closed through rubber magnetic strips in the absence of airflow, a barrier is formed, and particulate matters and condensate in the airflow are effectively blocked from directly contacting the sensitive membrane; when the airflow passes, the airflow pressure pushes away the rubber pieces, allows the airflow to pass, but blocks most of the pollutants, thereby protecting the sensitive membrane from being polluted, ensuring long-term stability and accuracy of the sensor; meanwhile, the protective plate is connected with the groove through a threaded ring, is convenient to disassemble and clean, and maintenance convenience is improved.

The present invention belongs to the field of sensor technology and relates to a low-power thin-film resistor-type hydrogen sensor and a method for preparing the same. The hydrogen sensor comprises a nanoarray hydrogen sensor, a resistor, and a storage capacitor; the branch where the nanoarray hydrogen sensor is located is connected in parallel with the branch where the storage capacitor is located; the branch where the nanoarray hydrogen sensor is located is provided with a resistor in series; and the branch where the nanoarray hydrogen sensor is located and the branch where the storage capacitor is located are powered by a power supply. The present invention utilizes the nanoarray hydrogen sensor to undergo an electrochemical reaction when excited by hydrogen, turning the nanoarray hydrogen sensor into a conductor, and utilizes the storage capacitor as a power supply to achieve low-power operation of the nanoarray hydrogen sensor. By controlling the operating voltage within a set range, it can ensure that the capacitor can quickly reach a stable state during each charge and discharge process, thereby improving the response speed and efficiency of the entire circuit, and the resistance value obtained by bridge measurement is more accurate and stable.

The application discloses a GaN-based hysteresis comparison circuit and relates to the field of semiconductor circuits.The circuit comprises a comparator circuit, a feedback circuit and a current mirror circuit which are connected with each other.The comparator circuit comprises a first N-type GaN device, a second N-type GaN device, a third N-type GaN device, a fourth N-type GaN device and a fifth N-type GaN device.The feedback circuit comprises a sixth N-type GaN device, a seventh N-type GaN device and an eighth N-type GaN device.The feedback circuit is composed of N-type GaN-based active devices instead of resistance passive devices, and the output signal is fed back to the gate of the seventh N-type GaN device, so that the circuit gain is improved, and the signal conversion time is reduced.

The invention discloses a SysML-based resistance-type superconducting current limiter design method and device. The method comprises the following steps: S1, obtaining design requirements of a resistance-type superconducting current limiter and carrying out requirement analysis; s2, analyzing a function logic architecture of the resistance type superconducting current limiter according to design requirements; s3, converting to obtain a physical architecture of the resistance type superconducting current limiter through design parameters and a functional logic architecture; and S4, outputting and obtaining a design result of the resistance type superconducting current limiter through a physical architecture and a set thermoelectric analogy algorithm. According to the method, the technical problems that in the prior art, the complexity of finite element simulation and numerical simulation is too high, and the demand analysis and architecture design in the design process are insufficient are solved, the resistance type superconducting current limiter can be rapidly designed, and the accuracy and consistency of the design result of the resistance type superconducting current limiter can be improved.

The application discloses a single-voltage detection power comparison circuit and belongs to the field of analog integrated circuit design.The circuit is composed of a switch circuit (1), a voltage difference to current circuit (2), a current mirror circuit (3), a voltage to current circuit (4) and a comparison output circuit (5).The switch circuit (1) comprises two complementary switches and five switch arrays; the voltage difference to current circuit (2) comprises a first operational amplifier, a first resistor, a load current mirror and a diode-connected MOS tube; the current mirror circuit (3) comprises six P-type MOS tubes and a pair of N-type MOS tubes; the voltage to current circuit (4) comprises a second operational amplifier, a second resistor, an N-type MOS tube and a diode-connected MOS tube; and the comparison output circuit (5) comprises a current adder-subtracter and two buffers.The application supports an MPPT dynamic tracking algorithm, the comparator output indicates the disturbance direction, the impedance matching and the control strategy are integrated, the adaptability to different DC-DC topologies is enhanced, the system design is simplified and the cost is reduced.

A control circuit for driving a relay to turn on and off quickly, comprising a relay. The first node of the relay coil is connected to a power supply through a boost circuit, and the second node of the relay coil receives a relay driving signal through a switch control circuit. The boost circuit includes a PNP-type triode, a first resistor, a second resistor, an energy storage capacitor, and a first diode. The emitter of the PNP-type triode and the positive pole of the first diode are connected to the power supply. The base of the PNP-type triode is connected to the power supply through the first resistor. The collector of the PNP-type triode and the negative pole of the energy storage capacitor are grounded through a third resistor. The negative pole of the first diode and the positive pole of the energy storage capacitor are connected to the first node of the relay coil. The switch control circuit includes an NPN-type triode and a fourth resistor. The base of the PNP-type triode is connected to the collector of the NPN-type triode and the second node of the relay coil through the second resistor and a voltage stabilizing diode. The base of the NPN-type triode receives the relay driving signal through the fourth resistor, and the emitter of the NPN-type triode is grounded.

The invention discloses a field-circuit coupling joint simulation modeling method for a resistance-type superconducting current limiter, which belongs to the technical field of simulation and comprises the following steps: constructing an electromagnetic heat calculation model of the resistance-type superconducting current limiter based on COMSOL; constructing a circuit simulation model of the resistance type superconducting current limiter power system based on Simulink; and performing joint simulation according to the electromagnetic heat calculation model and the circuit simulation model to obtain the average electric field intensity of the resistance type superconducting current limiter, the average temperature of each layer of the superconducting tape and the average current density of each layer of the superconducting tape. According to the method, through joint simulation modeling of COMSOL and Simulink, current distribution, temperature field distribution, magnetic field distribution, heating and temperature rise of the resistance type superconducting current limiter can be analyzed while parameters such as voltage and current in a circuit are analyzed.

The present disclosure relates to hybrid memory devices and methods for forming the same. A memory array includes hybrid memory cells, wherein each hybrid memory cell includes a transistor-type memory and a resistive-type memory. The transistor-type memory includes: a memory film extending over a gate electrode; a channel layer extending over the memory film; a first source / drain electrode extending over the channel layer; and a second source / drain electrode extending along the channel layer, and the resistive-type memory includes a resistive memory layer extending between the second source / drain electrode and the channel layer.

The application discloses a preparation process of high-resistance M-type hexagonal ferrite and a prepared product, and belongs to the technical field of permanent magnet ferrite. The method comprises the following steps: step a, dosing: dosing pre-sintered materials and auxiliary materials according to a weight ratio, wherein the auxiliary materials include SiO2 0.05%-0.2%, CaCO3 0.5%, Al2O3 0.14% and HBO3 0.3% according to the mass percentage of the pre-sintered materials; step b, ball milling: putting the dosed materials and water in the step a into a ball mill and ball milling; and step c, sintering: sintering the mixture after the ball milling in the step b at 1175 DEG C.-1235 DEG C. The high-resistance M-type hexagonal ferrite prepared by the method has the following performances: Br 390-420 mT, Hcb 270-300 KA / m, Hcj 240-380 KA / m, (BH) max 31-33 kJ / m 3 , and the resistance is greater than 21 MΩ.

A magnetoresistive random access memory ("MRAM" for short) device includes at least one MRAM array. Each MRAM array includes a reference cell and a reference generator that generates a reference voltage between a first voltage and a second voltage, the first voltage being a function of a first current flowing through the first reference cell and the second voltage being a function of a second current flowing through the second reference cell, the first reference cell and the second reference cell are a pair of reference cells storing complementary values in a row of the MRAM array. Reference voltage can be automatically centered and track reading current changes of all PVT angles, and the reference voltage does not need to be adjusted. In some embodiments, the reference generator is used in cooperation with a current detection amplifier, and correct read data of all PVT angles can be reliably output.

The application discloses a resistance testing method, and relates to the technical field of intelligent testing, and comprises the following steps: step S100, testing any resistance model of resistance, independently analyzing the testing result, and obtaining self characteristics; step S200, performing positive testing and reverse testing on the resistance to be tested according to the testing method, and obtaining positive result and reverse result; and step S300, dividing the grade of the resistance to be tested according to the positive result, the reverse result and the self characteristics. Through screening of effective historical data, the application improves the scientificity of subsequent analysis and the rationality of testing parameters, avoids irreversible damage to the resistance, improves the economy of testing, eliminates one-way system errors such as contact resistance, lead resistance and thermoelectric potential through mean value taking of positive and reverse testing and difference value analysis.

The invention relates to the technical field of integrated circuits and provides a differential digital-to-analog converter. The differential digital-to-analog converter comprises two groups of N-bit resistor arrays and three-state switch arrays which have the same resistor array structure. The differential digital-to-analog converter provides a three-level sectional structure comprising three different reference voltages, reduces the area overhead of a switch, improves the conduction impedance matching, avoids the introduction of an additional dynamic circuit, facilitates the reduction of static power consumption, and improves the reliability of the converter. And application of a static circuit and related application of a high-precision resistance type digital-to-analog converter are facilitated.

Provided is a complementary sensors-integrated interface circuit and a differential circuit using the same. The complementary sensors-integrated interface circuit includes: a first sensor having a sensing characteristic for a detection target material; and a second sensor having a sensing characteristic complementary to that of the first sensor for the detection target material, wherein the first sensor is composed of an FET-type sensor, the second sensor is composed of an FET-type sensor or a resistor-type sensor, and the first sensor and the second sensor are connected in series. The interface circuit having the above-described configuration increases the change in output voltage, thereby improving the sensing sensitivity. The complementary sensors-integrated interface circuit is characterized in that it serves as an amplification circuit. In addition, a complementary sensors-integrated differential interface circuit uses the aforementioned complementary sensors-integrated interface circuit, thereby serving as a differential amplifier circuit, reducing noise and improving sensitivity.

The invention discloses a resistive readout unit circuit for FLASH memory calculation, which relates to the technical field of integrated circuits, and comprises a conversion module and a quantization module, the conversion module comprises a positive weight current conversion unit and a negative weight current conversion unit which have the same structure, the input end of the conversion module is respectively connected with a positive weight bit line and a negative weight bit line, and the output end of the conversion module is connected with the quantization module; each circuit comprises an operational amplifier, a driving transistor, a compensation resistor, a compensation capacitor and a compensation transistor; the quantization module comprises two sampling switches, two CDACs, a comparator and an SAR logic circuit, the input ends of the two sampling switches are connected with the output ends of the positive weight resistor module and the negative weight resistor module respectively, and the output ends of the two sampling switches are connected with the upper polar plates of the two CDACs and the positive input end and the negative input end of the comparator respectively. The resistance-type read-out unit circuit can stably perform driving and analog-to-digital conversion on the storage current which changes rapidly with a small area and a small power consumption overhead.

The invention discloses a temperature transmitter response time testing device and method, and relates to the technical field of temperature transmitter calibration, and the device comprises a tested temperature transmitter without a temperature sensor, a data recorder, a change-over switch, a first input signal, and a second input signal. The first input signal and the second input signal are connected to a first input binding post and a second input binding post of the change-over switch respectively. The input signal I and the input signal II are temperature signals of the same type, and the input signal I and the input signal II are thermocouple type potential signals or thermal resistance type resistance signals; an output binding post of the change-over switch is electrically connected with the input end of a tested temperature transmitter, and the output end of the tested temperature transmitter is electrically connected with the input end of a data recorder. According to the invention, the blank of the device and the method for testing the response time of the temperature transmitter without a temperature sensor is filled, and the test device and the method are proved by practice.

The application discloses a kind of endoscopic medical instruments, comprising: main machine and component, wherein component is detachably mounted to main machine, main machine includes identification circuit, component includes identity confirmation structure, identity confirmation structure includes following three types: resistance type, chip type or resistance chip type;Identification circuit can identify chip and identify resistance resistance value to judge the type of identity confirmation mechanism.The endoscopic instrument component of the application can be compatible with different types of components, and quickly identify component type, execute corresponding procedures, which can improve the work efficiency of doctors.

In the described example, the R2R digital-to-analog converter includes a plurality of arms and a voltage regulator (110). Each arm includes an arm switch (130) having a p-channel MOSFET (PFET) switch (132) and an NFET switch (134). The voltage regulator includes a differential amplifier (314), a p-ladder (308) including N cascode-coupled PFETs (306) and having first and second ends, an n-ladder (318) including γ×N cascode-coupled NFETs (316) and having first and second ends, a first resistor (310), and a second resistor (resistor γ×R) (312). The first p-ladder end is coupled to a first terminal of the first resistor. The second terminal of the first resistor is coupled to the input of the differential amplifier and the first terminal of the second resistor, the second terminal of the second resistor is coupled to the first n-ladder end, and the output of the differential amplifier is coupled to the second n-ladder end to provide the gate voltage of the NFET switch.

An RTD (Resistant Temperature Detector) test terminal and device are disclosed, relating to the field of PLC testing technology. Addressing the problems of excessive manual wiring and switching operations, low testing efficiency, susceptibility to connection errors or omissions, and difficulty in achieving rapid and stable multi-channel measurements in existing PLC testing processes, this invention provides an RTD test terminal. The terminal includes a main body with a circuit board, probes and pin sleeves, a cover plate, an upper cover plate, a back clamp bracket, a back clamp, a back clamp baffle, and pin sleeve slots. The probes and pin sleeves are used to contact the tested terminal. The circuit board is used for electrical connection with the probes and switching output levels. The cover plate and upper cover plate are used for encapsulation, and the back clamp bracket, back clamp, and back clamp baffle are used for clamping and mounting. This test terminal is suitable for rapid testing and switching measurements of RTD signal channels in PLC cabinets.

The application belongs to the technical field of directional coupler, and is a resistance type wideband directional coupler based on transmission line structure, which comprises two uncoupled uniform transmission lines, the two lines have a common reference ground, and are spatially isolated by a split surface, the split surface is perpendicular to the conductor plane between the connecting lines of the two uncoupled uniform transmission lines; an input port, a straight-through output port, a coupled output port and an isolation port are arranged on the two lines respectively. The two lines are both composed of quarter wavelength transmission line groups of the same order, one is a main transmission line, and the other is a coupled transmission line, and the characteristic impedances of the two lines are the same as the impedance of the external port. There is a coupling resistor across the quarter wavelength coupled transmission line group. The transmission line electric length between adjacent coupling resistors is a quarter wavelength; the application can reduce the requirement for processing error due to the symmetrical and simple structure, and has the characteristics of low reflection coefficient and ultra-wideband operation.