Dual-Gated Group III-V Merged Transistor

Abstract

There are disclosed herein various implementations of a group III-V merged cascode transistor. Such a group III-V merged cascode transistor includes a group III-V body disposed over a substrate and configured to produce a two-dimensional electron gas (2DEG). The group III-V body includes a group III-V barrier layer situated over a group III-V channel layer, and a source electrode and a drain electrode. The group III-V merged cascode transistor also includes an enable gate disposed in a recess extending substantially through the group III-V barrier layer, and an operational gate disposed over the group III-V barrier layer, the operational gate not being in physical contact with the enable gate.

Description

[0001]The present application claims the benefit of and priority to a provisional application entitled “Dual Gated Merged Cascode Device,” Ser. No. 61 / 913,156 filed on Dec. 6, 2013. The disclosure in this provisional application is hereby incorporated fully by reference into the present application.BACKGROUND[0002]I. Definition[0003]As used herein, the phrase “group III-V” refers to a compound semiconductor including at least one group III element and at least one group V element. By way of example, a group III-V semiconductor may take the form of a III-Nitride semiconductor. “III-Nitride” or “III-N” refers to a compound semiconductor that includes nitrogen and at least one group III element such as aluminum (Al), gallium (Ga), indium (In), and boron (B), and including but not limited to any of its alloys, such as aluminum gallium nitride (AlxGa(1-x)N), indium gallium nitride (InyGa(1-y)N), aluminum indium gallium nitride (AlxInyGa(1-x-y)N), gallium arsenide phosphide nitride (GaAsa...

AI Technical Summary

Benefits of technology

This patent describes a new type of transistor that has two gates and is made using a specific material called group III-V. The transistor can be controlled by these gates and has certain technical advantages.

Problems solved by technology

However, conventional approaches for implementing such merged transistors typically result in one of the depletion mode or the enhancement mode group III-V devices being susceptible to voltage breakdown due to “spillover” of the 2DEG and the possible trapping of electrons at an interface of the affected device.

Images