3 results about "Lag time" patented technology

This invention relates to the field of structural engineering testing and discloses a method for the coordinated acquisition and fusion of deflection and strain in static load tests of structural components. The method includes: monitoring local strain physical quantities and calculating real-time strain rate; identifying the strain mutation initiation signal when the strain rate exceeds a threshold; retrieving the relative physical span between sensing nodes and the intrinsic stress wave velocity of the material; calculating the physical lag time; sending a hardware interrupt pulse carrying a time delay parameter to the deflection sensing node; driving the hardware circuit to activate a timing response matching the physical lag time; and capturing the macroscopic deflection physical quantity at the end of the timing. This invention eliminates the perception phase misalignment caused by spatial span by constructing a hardware sampling alignment mechanism driven by physical causality, ensuring that the acquired data conforms to the structural mechanics constitutive relationship, and improving the system's accuracy in identifying structural damage evolution characteristics.

The application provides a cross-clock domain time information correction method and a distributed system thereof. The method comprises the following steps: a sub-node sends a digital signal carrying its own clock and data information to a master node, and then the master node recovers the sub-node clock and data; the master node is configured with a sub-node clock counter and a master node clock counter; the master node samples one clock by using the other clock, and when the lag time between the two clocks reaches a single period of the clock with a higher frequency, the sub-node clock counter is adjusted to keep the two clock counters consistent; and the time stamp of the data of the sub-node in the master node clock domain is obtained through the sub-node clock counter and the master node clock. The application has a simple structure, saves the calculation cost, and has high time measurement precision.

Accepted events are processed. Each accepted event is associated with a respective ingested timestamp, a respective processing-start timestamp, and a respective processing-complete timestamp. Events are accepted at a rate of a target rate limit. A current error value is obtained as a difference between a target lag time and a second value. The target lag time indicates a configured maximum time within which an accepted event is to be processed. The second value is an average of differences between the respective processing-complete timestamps and the respective ingested timestamps. A base throttle is obtained based on previous error values and the current error value. The base throttle is smaller than the target rate limit and indicates a maximum number of events per a unit of time to be accepted for processing. Subsequent events are accepted at a new rate obtained from the base throttle.