Nitride-based transistors and fabrication methods with an etch stop layer

Abstract

A III-Nitride field-effect transistor, specifically a HEMT, comprises a channel layer, a barrier layer on the channel layer, an etch stop layer on the cap layer, a dielectric layer on the etch stop layer, a gate recess that extends to the barrier layer, and a gate contact in the gate recess. The etch stop layer may reduce damage associated with forming the recessed gate by not exposing the barrier layer to dry etching. The etch stop layer in the recess is removed and the remaining etch stop layer serves as a passivation layer.

Description

FIELD OF THE INVENTION [0001] The present invention relates to semiconductor devices and in particular relates to transistors, such as high electron mobility transistors (HEMT), that incorporate nitride-based active layers and a recessed gate structure, and methods of fabricating same. BACKGROUND [0002] Materials such as silicon (Si) and gallium arsenide (GaAs) have found wide application in semiconductor devices for lower power and (in the case of Si) lower frequency applications. These, more familiar, semiconductor materials may not be well suited for higher power and / or high frequency applications, however, because of their relatively small bandgaps (e.g., 1.12 eV for Si and 1.42 for GaAs at room temperature) and / or relatively small breakdown voltages. [0003] In light of the difficulties presented by Si and GaAs, interest in high power, high temperature and / or high frequency applications and devices has turned to wide bandgap semiconductor materials such as silicon carbide (2.996...

AI Technical Summary

Benefits of technology

[0010] Some embodiments of the present invention provide III-nitride based transistors and methods of making the same that utilize an etch stop layer to protect underlying layers from etch damage associated with the formation of recesses. In some embodiments, the recess may be used for a recessed gate contact.

[0015] In still further embodiments of the present invention, forming a gate recess includes patterning a mask layer on the dielectric layer to have an opening corresponding to the gate recess and etching the dielectric layer to the etch stop using the patterned mask layer as an etch mask. The etch stop layer may reduce damage in the gate recess by isolating and protecting the surface of the barrier layer during the dielectric layer etch. Forming the gate recess further includes removing the etch stop layer in the gate recess thereby extending the gate recess to the barrier layer.

Problems solved by technology

These, more familiar, semiconductor materials may not be well suited for higher power and / or high frequency applications, however, because of their relatively small bandgaps (e.g., 1.12 eV for Si and 1.42 for GaAs at room temperature) and / or relatively small breakdown voltages.

On the other hand, an etching process used to form a recessed gate structure may damage the underlying barrier layer(s).

Damage to the barrier layer may result in the formation of a high density of surface states or traps that adversely affect device operation.

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