Automatic verification platform and method for on-chip memory management unit fault-tolerant structure

Abstract

The invention provides an automatic verification platform and method for an on-chip memory management unit fault-tolerant structure. The automatic verification platform and method can conduct random fault injection verification on the fault-tolerant structure and are high in verification coverage rate. The platform comprises a debugging host and a to-be-tested host connected through a serial port. The debugging host is used for flow control verification, encoding result checking, fault injection, decoding result checking in the verification process, and monitoring and debugging of a processor. The on-chip memory stack fault-tolerant structure is integrated in the to-be-tested host and used for generation of check codes, decoding verification after decoding logic and fault injection and loading of an automatic verification program for the memory stack fault-tolerant structure. The memory stack fault-tolerant structure comprises a memorizer control module, a fault-tolerant module, a selector and a memory stack. The memorizer control module and the fault-tolerant module conduct read-write control over the memory stack through the selector to control the working mode and the failure mode of the on-chip memory stack fault-tolerant structure.

Description

technical field [0001] The invention relates to the field of fault testing of single event flipping, in particular to an automatic verification platform and method for fault-tolerant structures of on-chip storage management units. Background technique [0002] In recent years, with the rapid development of semiconductor technology, the demand for the scale and performance of integrated circuits has continued to increase. In order for SOC to be suitable for the deep space field, appropriate anti-radiation hardening technology must be adopted to solve the reliability problems caused by single event effects. [0003] The anti-flip and fault-tolerant design technology of the spaceborne system can only be verified on the ground to ensure the reliability of the design. The current methods are mainly through single-event irradiation test and simulation. The cost of single-event irradiation test is high. The cycle is long, and it is not easy to be used as an effective test method; t...

AI Technical Summary

Problems solved by technology

Although this method realizes the verification of SRAM FPGA fault tolerance combined with hardware and software, it needs its structure to implement fault injection and result comparison through dual FPGAs. Compared with FPGA2, if it is replaced with a chip, the test cost is higher

Images