Patents
Literature
Patsnap Copilot is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Patsnap Copilot

53results about How to "Minimize charge" patented technology

Volume charge density measuring system

A capacitive sensor is shielded against external electric fields to maximize measurement accuracy. The sensor may include two coaxial, tubular conductors with a chamber between them into which a material sample to be measured is introduced. A measurement circuit connected to the sensor may include a reference oscillator that oscillates at a constant frequency and a test oscillator that oscillates at a frequency responsive to sensor capacitance. The circuit may display a value responsive to the difference between the test and reference frequencies. The circuit may also reverse the polarity of the signal applied to the sensor to minimize charge buildup, a phase-locked loop frequency measuring circuit, a temperature compensating circuit, and a non-linearity compensating circuit. The indicating circuit that displays a representation of the measured capacitance may display a continuous-scale or proportional representation or may display a binary or "go-nogo" representation. An alternative sensor of the system includes coaxial, finned inner and outer conductors that intermesh to maximize capacitive surface area. Another alternative sensor includes two parallel, plate-like conductors. The sensor system may be used to measure volume charge density of a fluid or parameters responsive to changes in volume charge density, such as flow velocity.
Owner:JOFRACH L L C

Insulated gate bipolar transistor

An IGBT is provided comprising at least two first cells (1, 1′), each of which having an n doped source layer (2), a p doped base layer (3), an n doped enhancement layer (4), wherein the base layer (3) separates the source layer (2) from the enhancement layer (4), an n− doped drift layer (5) and a p doped collector layer (6). Two trench gate electrodes (7, 7′) are arranged on the lateral sides of the first cell (1, 1′).
The transistor comprises at least one second cell (15) between the trench gate electrodes (7, 7′) of two neighboured first cells (1, 1′), which has on the emitter side (90) a p+ doped well (8) and a further n doped enhancement layer (40, 40′) which separates the well (8) from the neighboured trench gate electrodes (7, 7′). An insulator layer stack (75) is arranged on top of the second cell (15) on the emitter side (90) to insulate the second cell (15) and the neighboured trench gate electrodes (7, 7′) from the metal emitter electrode (9), which consists of a first insulating layer (73) and a second insulating layer (74), wherein the insulator stack (75) has a thickness on top of the well (8) of a first layer thickness plus the second insulating layer thickness and a thickness on top of the gate layer (70, 70′) of the second insulating layer thickness, wherein each thickness of the first insulating layer (73) and the second insulating layer (74) is at least 700 nm.
Owner:HITACHI ENERGY SWITZERLAND AG
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products