On-chip RAM built-in self-testing method and circuit

Abstract

The invention discloses an on-chip RAM built-in self-testing method and circuit. The method comprises the following steps: configuring an initial address of a test; operating each address in a preset range from the initial address; writing zero according to the ascending sequence of the addresses; and carrying out twice zero-read and twice one-write operations according to the descending sequence of addresses; carrying out one-read operation, zero-write operation, zero-read operation and one-write operation according to the ascending sequence of addresses; carrying out twice one-write operations and twice zero-read operations; carrying out zero-read operation, one-write operation, one-read operation and zero-write operation; and carrying out zero-read operation. In the operation processes, when the read-out data of a certain tested address is not accordant to expected data, the tested address is determined to be failed, and an error mark and the tested address with failure are output after testing is completed. The on-chip RAM built-in self-testing method and circuit can be used for solving the problem that the static failure of a single unit cannot completely detected in the prior art.

Description

technical field [0001] The invention relates to the field of chip detection, in particular to an on-chip RAM built-in self-test method and circuit. Background technique [0002] With the increasing scale and integration of Random-Access Memory (RAM) in integrated circuit products, more and more complex RAMs will inevitably appear in the manufacturing process. RAM physical defect. Chips with failed memory cells will cause unpredictable errors at the product level, causing the cost of correction to skyrocket. Therefore, testing and screening RAM memory with high coverage at the wafer stage has become an important part of the entire life cycle of the chip. How to quickly locate defective units through wafer testing, improve detection coverage, reduce test time, and improve test efficiency are issues that need to be analyzed and solved in depth at the beginning of chip design. [0003] A detection algorithm commonly used in RAM built-in self-test (Built-in Self Test, BIST) ci...

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Problems solved by technology

[0012] The present invention provides an on-chip RAM built-in self-test method and circuit, which are used to solve the problems in the prior art that the March

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