The invention discloses a
clock generation circuit for an analog-to-digital circuit, which comprises a
clock stabilizing circuit and a two-phase non-overlapping
clock generation circuit. The clock stabilizing circuit comprises a clock stabilizing loop and a feedback
signal generation circuit. In the feedback
signal generation circuit, a
control signal is generated by an active low-pass filter to control an N tube current modulation
inverter, the clock stabilizing loop is used for generating a stable
clock signal, and by a filtering technology and a current modulation technology, accurate modulation on a feedback
signal is implemented. In the clock stabilizing loop, by a loop structure, a duty ratio of an output clock can be reduced; under the regulation of the feedback signal, by pulling up a PMOS tube MP1, the duty ratio of the output clock is increased, and finally, the duty ratio of 50% of the output clock is achieved; and the clock is stabilized and vibration is reduced. According to the clock generation circuit disclosed by the invention, the clock stabilizing circuit can be integrated into an ADC circuit; and by adopting the structure disclosed by the invention,
clock signal quality can be obviously improved, the strict requirement of an ADC for clock quality is reduced, and a signal-to-
noise ratio of the ADC is improved.