Wide-range low-jitter high-precision clock signal proportion stabilizer circuit and adjusting method

Abstract

The invention discloses a wide-range low-jitter high-precision clock signal ratio stabilizer circuit, which is characterized in that an original clock signal generates a narrow pulse signal with a corresponding duty ratio through a pulse generation circuit, one path of the narrow pulse signal enters a capacitor discharge current regulation circuit, and the other path of the narrow pulse signal enters a pulse detection and reduction circuit; the two narrow pulse signals generate reduction square waves through the pulse detection reduction circuit, the reduction square waves enter the capacitor discharge current adjusting circuit, the descending slope of triangular wave signals output by an inverter is adjusted, the triangular wave signals enter the clock signal shaping circuit, and then the phases of the narrow pulse signals are adjusted. And finally, the two narrow pulse signals pass through a pulse detection and reduction circuit to generate reduction square waves with the duty ratio of 1: 1. The circuit well solves the problem of duty ratio of an input clock, and provides an accurate clock signal for a core circuit of the converter. The invention also provides a clock signal adjusting method realized by adopting the wide-calibration-range low-jitter high-precision clock signal proportion stabilizer circuit.

Description

technical field [0001] The invention relates to a wide calibration range low-jitter high-precision clock ratio stabilizer circuit, which belongs to the technical field of analog-to-digital converters. Background technique [0002] The converter is a key component of the interface between the analog system and the digital system, and is widely used in industry, communication, radar and other fields. In recent years, the high-speed development of converters has led to the continuous improvement of the sampling rate requirements. In ultra-high-speed converters, most converter circuits use multi-channel time interleaving technology to improve the sampling rate of the overall circuit. Multi-channel time interleaving technology must Signal sampling and digital-to-analog conversion are carried out in strict accordance with the time sequence, so strict requirements are placed on the clock circuit. With the improvement of manufacturing process technology, the proportion of clock ris...

AI Technical Summary

Problems solved by technology

The circuit has a wide calibration range and can adjust the clock signal of 20%-80% clock duty cycle. The calibration output clock signal has high precision and low jitter characteristics, which improves the dynamic performance of the converter and solves the conversion rate caused by clock jitter. and the problem of degraded signal-to-noise ratio

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