Clock generation circuit used in analog-to-digital converter (ADC) with high speed and high precision

Abstract

The invention discloses a clock generation circuit used in an analog-to-digital converter (ADC) with a high speed and high precision. The clock generation circuit comprises: a low noise amplification and shaping circuit, a pulse width controller, a DLL with pulse width calibration, a biphase non-overlapping clock generation circuit and a clock buffer. A voltage-controlled delay line (VCDL) with pulse width adjustment is designed in the DLL with the pulse width calibration. The VCDL can realize clock signal time delay and pulse width control based on a cascade group comprising same M improvement delay units. The DLL with the pulse width calibration and the biphase non-overlapping clock generation circuit together form a time-delay control and pulse width adjustment loop. Therefore, working sequences of an ADC sampling circuit and a quantizer can be synchronized and stable processing to an input clock duty ratio can be realized. By using the technical scheme of the invention, a bandwidth requirement to an ADC driving circuit can be reduced; difficulty for designing the system and power consumption can be reduced; realization precision of the ADC quantizer can be improved.

Description

technical field [0001] The present invention relates to analog-to-digital converter technology, in particular to a clock generating circuit for high-speed and high-precision analog-to-digital converter. Background technique [0002] With the advent of the new generation of wireless communication era, the digital intermediate frequency receiver in the communication system puts forward higher requirements on the speed and accuracy of the analog-to-digital converter ADC, and the ADC presents a trend of high speed and high precision development. For high-speed and high-resolution ADCs, the quantizer is required to achieve high settling accuracy in a short period of time. Since the circuit in the quantizer is established in two phases alternately, it is required to control the work of the quantizer. The non-overlapping clocks have the same pulse width to optimize the operating speed of the entire quantizer. The higher the conversion speed of the ADC, the more demanding the settl...

AI Technical Summary

Problems solved by technology

[0008] 2) The switching sampling action controlled by the falling edge of clock cks is ahead of the falling edge of f1b, which may interfere with the signal sampling controlled by the falling edge of f1b in quantizer 4, resulting in a decrease in its accuracy

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