High-speed receiver circuit of DDR4 standard

Abstract

The invention discloses an input receiver circuit of a DDR4 standard. The input receiver circuit comprises a first transistor MP1, a second transistor MP2, a third transistor MP3, a fourth transistorMP4, a fifth transistor MP5, a sixth transistor MN1, a seventh transistor MN2, an eighth transistor MN3, a ninth transistor MN4, a first phase inverter, a second phase inverter, a third phase inverterand a fourth phase inverter, wherein MN4 and MP5 form a duty ratio adjusting circuit for improving the output duty ratio. The high-speed receiver circuit of the DDR4 standard has the advantages of asimple structure, high transmission bandwidth, low transmission delay and the like.

Description

technical field [0001] The invention relates to integrated circuit design technology, in particular to a DDR4 standard high-speed receiver circuit. Background technique [0002] The bandwidth and interface speed of high-density dynamic memory (DRAM) buses are important indicators of system performance, and the industry continues to push the boundaries of system design constraints to achieve higher memory interface data transfer rates. Compared with the previous DDR3 SDRAM in terms of capacity, speed and compatibility, DDR4 SDRAM has been greatly improved, and has been widely used in many fields, but there are still many problems in the design of DDR4 receiver circuits, for example: due to different level standards With the improvement of the transmission rate, the traditional DDR3 standard receiver circuit structure is no longer suitable for the design of the DDR4 standard receiver; the circuit structure of the DDR4 standard receiver designed by others is relatively complica...

AI Technical Summary

Problems solved by technology

Compared with the previous DDR3 SDRAM in terms of capacity, speed and compatibility, DDR4 SDRAM has been greatly improved, and has been widely used in many fields, but there are still many problems in the design of DDR4 receiver circuits, for example: due to different level standards With the improvement of the transmission rate, the traditional DDR3 standard receiver circuit structure is no longer suitable for the design of the DDR4 standard receiver; the circuit structure of the DDR4 standard receiver designed by others is more complicated, and the input signal is amplified by using a multi-stage differential amplifier. And it needs to have an additional bias voltage generating circuit, which has the disadvantages of large layout area, large delay and high power consumption, and the duty cycle of the output signal is greatly affected by process deviation, temperature change and voltage fluctuation

Images