A Duty Cycle Stable Digitally Controlled Single-Stage Multi-Clock Phase Interpolator

Abstract

The invention discloses a digital control single-stage multi-clock phase interpolator with a stable duty cycle. The phase interpolator has input clock signals CKI and CKQ, comprises a digital controlselection unit, a digital phase interpolation unit and a data selector, and is mainly used in various high-speed clock data recovery acquisition systems to provide an accurate multi-phase clock in thesystems for the systems to select the optimal sampling clock phase. The digital control single-stage multi-clock phase interpolator with a stable duty cycle has a simple requirement for input, requires only two digital input high-low level signals with a phase difference, has a simple internal sequential control logic circuit, and can output a high-precision multi-phase clock with a constant dutycycle.

Description

technical field [0001] The invention relates to the technical field of phase interpolation, in particular to a duty ratio stable digital control single-stage multi-clock phase interpolator. Background technique [0002] Clock phase interpolator can provide accurate multi-phase clock phase, widely used in mixed-signal interface circuit system, especially in high-speed clock data recovery system (CDR). The system recovers a reasonable clock for sampling data by selecting an accurate clock phase to ensure accurate sampling data. [0003] There are several ways to realize the phase interpolator: analog phase interpolator based on current mode logic (CML) unit; pure digital phase interpolator based on inverter; digital phase interpolator based on DLL. [0004] The CML-based analog phase interpolator can provide high bandwidth and good linearity, but because the interpolator based on the CML unit requires a fixed tail current, it needs to consume large power consumption and area,...

AI Technical Summary

Problems solved by technology

However, the difference between the two input phases of the digital phase interpolator based on the inverter cannot be too large. When the difference between the two phases is much greater than the input rise and fall delay, the interpolation function will fail

Therefore, this purely digital phase interpolator can only handle two inputs with a small phase difference, and its application range is limited

[0006] Finally, regarding the phase interpolator of CMOS level, multiple phase input control clocks and complex timing control circuits are required, which increases the complexity of the circuit and increases the requirements for input; in addition, it mainly performs interpolation processing on the falling edge of the output clock. , the rising edge basically does not change. When the phase difference between the two clocks required for interpolation is relatively large, the duty cycle of the output clock changes. In specific applications, such as clock sampling systems, the clock duty cycle is very demanding

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