Clock generation circuit for analog-to-digital converter

Abstract

The invention discloses a clock generation circuit for an analog-to-digital circuit, which comprises a clock stabilizing circuit and a two-phase non-overlapping clock generation circuit. The clock stabilizing circuit comprises a clock stabilizing loop and a feedback signal generation circuit. In the feedback signal generation circuit, a control signal is generated by an active low-pass filter to control an N tube current modulation inverter, the clock stabilizing loop is used for generating a stable clock signal, and by a filtering technology and a current modulation technology, accurate modulation on a feedback signal is implemented. In the clock stabilizing loop, by a loop structure, a duty ratio of an output clock can be reduced; under the regulation of the feedback signal, by pulling up a PMOS tube MP1, the duty ratio of the output clock is increased, and finally, the duty ratio of 50% of the output clock is achieved; and the clock is stabilized and vibration is reduced. According to the clock generation circuit disclosed by the invention, the clock stabilizing circuit can be integrated into an ADC circuit; and by adopting the structure disclosed by the invention, clock signal quality can be obviously improved, the strict requirement of an ADC for clock quality is reduced, and a signal-to-noise ratio of the ADC is improved.

Description

technical field [0001] The invention relates to the field of analog integrated circuits, in particular to a clock generating circuit structure that can be used in digital and analog mixed signal circuits. Background technique [0002] In the process of human beings using technology and wisdom to explore nature, the first signals obtained are analog signals, while computers can only process digital signals. It is necessary to use an analog-to-digital converter to quantize the analog signals that exist widely in nature into digital signals for people to use computers for processing and transmission. Therefore, the analog-to-digital converter is a bridge between the analog world and the digital world, and has important use value and broad application prospects. [0003] With the continuous development of ADC (Analog-to-Digital Converter) toward high speed and high precision, the error caused by the phase noise caused by the sampling clock jitter to the sample-and-hold circuit ...

AI Technical Summary

Problems solved by technology

The jitter generated by the clock signal will cause the internal circuit of the ADC to incorrectly trigger the sampling time, resulting in missampling of the analog input signal in amplitude, thereby deteriorating the signal-to-noise ratio of the ADC

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