A duty cycle stable and low jitter clock circuit

Abstract

The invention discloses a clock circuit with stable duty cycle and low jitter. The whole clock circuit is composed of a clock driving amplifier module, a charge pump module, an output clock falling edge trigger circuit module, an output clock rising edge trigger circuit module, an output clock waveform stabilization circuit module and a charge pump phase-locked loop module. The clock waveform stabilization circuit generates a complete output clock according to the edge control pulse generated by the rising edge and falling edge control circuit; the falling edge trigger circuit keeps the falling edge of the output clock consistent with the falling edge of the input clock; the rising edge trigger circuit can be based on the input clock. The duty cycle detection result is based on the falling edge of the output clock, and the position of the rising edge of the output clock is adjusted so that the duty cycle of the output clock is finally stabilized to 50%; the charge pump phase-locked loop receives the output clock of the output clock waveform stabilization circuit module, Generates high-speed low-jitter clock signals. The clock circuit can meet the stringent requirements for clock signals in high-frequency applications.

Description

technical field [0001] The invention relates to a clock circuit with stable duty ratio and low jitter, which belongs to the field of integrated circuit clock systems and is mainly used to stabilize the duty ratio of high-speed clock signals, reduce clock jitter, and effectively improve the performance of the clock system. Background technique [0002] With the rapid development of communication technology, computer technology, and microelectronics technology, the application of electronic technology has penetrated into every corner of the economic and national defense fields, and various high-performance electronic products continue to emerge. A / D converters will be widely used in data processing and acquisition channels of sensors, and are the core components of electronic systems in these application fields. In a conventional communication system, the receiver generally uses multi-stage down conversion to convert the radio frequency signal to a center frequency low enough ...

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Problems solved by technology

[0004] like figure 1 As shown, ideally, the duty cycle of the clock should be 50% without any jitter. In actual situations, the clock signal source is usually generated and supplied by an external crystal oscillator, and its duty cycle cannot be obtained stably. and accuracy, and cannot meet the requirements of the overall A / D converter system

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