Phase-locked loop with quick response

Abstract

The invention discloses a phase-locked loop with quick response, which comprises a circuit for converting charge pump charging impulse output by a phase frequency detector into slope voltage, a circuit for converting the slope voltage into slope current and a minimum pulse width detection circuit. The quick locking function is realized by linearly increasing the charge pump charging current during the charging of a charge pump. At the same time, when the pulse width is less than a certain value, the function of shielding the current of the slope charge pump ensures that the phase noise is not affected. In the phase-locked loop, the bandwidth of a loop is broadened by linearly increasing the charge pump charging current of the phase-locked loop of the charge pump; and the quick startup characteristics and the phase noise are well guaranteed by recovering the current to an original value in a locking state at the same time.

Description

technical field [0001] The present invention relates to semiconductor integrated circuits, in particular to frequency generation and frequency synthesis applications for high-speed processors, broadband data communication systems, radars, space electronic equipment and high-speed digital electronic systems. Background technique [0002] The current high-speed development of high-performance processors and wireless communications poses new challenges in terms of high-speed and low-noise phase-locked loops. However, in a specific design, these two characteristics often conflict. If you simply consider the fast locking feature, it can be realized by increasing the loop bandwidth of the phase-locked loop, but this makes the phase noise unrestricted. If the loop bandwidth is reduced, although the phase noise is suppressed, the loop response time will slow down again. In response to this contradiction in design, some technologies in this area have been reported at home and abroa...

AI Technical Summary

Problems solved by technology

However, in specific designs, these two characteristics often conflict

If only considering the fast locking characteristics, it can be realized by increasing the loop bandwidth of the phase-locked loop, but this makes the phase noise unrestrained

If the loop bandwidth is reduced, although the phase noise is suppressed, the response time of the loop will be slower

In response to this contradiction in design, some technologies in this area have been reported at home and abroad, such as fast locking through double-loop control, switched capacitor filters, etc., but there are certain limitations in terms of circuit complexity and phase noise. defect

Images