Clock circuit with stable duty ratio and low jitter

Abstract

The invention discloses a clock circuit with a stable duty ratio and low jitter. The whole clock circuit comprises a clock driving amplifier module, a charge pump module, an output clock falling edgetriggering circuit module, an output clock rising edge triggering circuit module, an output clock waveform stabilization circuit module and a charge pump phase-locked loop module. The clock waveform stabilization circuit generates a complete output clock according to edge control pulses generated by rising edge and falling edge control circuits; the falling edge triggering circuit enables a falling edge of an output clock and a falling edge of an input clock to maintain consistent; the rising edge triggering circuit can take the output clock falling edge as a reference to adjust the output clock rising edge position according to a duty ratio detection result of the input clock, so that the duty ratio of the output clock is finally stabilized to 50%; and the charge pump phase-locked loop receives the output clock of the output clock waveform stabilization circuit module and generates a high-speed low-jitter clock signal. The clock circuit can meet a rigorous requirement for a clock signal in high-frequency application.

Description

technical field [0001] The invention relates to a clock circuit with stable duty ratio and low jitter, which belongs to the field of integrated circuit clock systems and is mainly used to stabilize the duty ratio of high-speed clock signals, reduce clock jitter, and effectively improve the performance of the clock system. Background technique [0002] With the rapid development of communication technology, computer technology, and microelectronics technology, the application of electronic technology has penetrated into every corner of the economic and national defense fields, and various high-performance electronic products continue to emerge. A / D converters will be widely used in data processing and acquisition channels of sensors, and are the core components of electronic systems in these application fields. In a conventional communication system, the receiver generally uses multi-stage down conversion to convert the radio frequency signal to a center frequency low enough ...

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Problems solved by technology

[0004] like figure 1 As shown, ideally, the duty cycle of the clock should be 50% without any jitter. In actual situations, the clock signal source is usually generated and supplied by an external crystal oscillator, and its duty cycle cannot be obtained stably. and accuracy, and cannot meet the requirements of the overall A / D converter system

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