7 results about "Dual pulse" patented technology

This invention discloses a method for enhancing and controlling the radiation of an LPP-EUV light source based on dual-pulse spatiotemporal co-constraint, belonging to the field of semiconductor manufacturing technology. This invention obtains a spatiotemporal reference by real-time monitoring of a liquid metal droplet, uses a pre-pulse laser to induce target material deformation into a fogged target cloud, and combines high-speed imaging and a hydrodynamic model to predict the time and coordinates of the target cloud's energy absorption peak. It dynamically adjusts the delay time and optical axis direction of the main pulse laser to achieve dual-pulse spatiotemporal co-constraint, and constructs a closed-loop control system through a recursive least squares algorithm with a dynamic forgetting factor. This invention effectively improves the extreme ultraviolet light conversion efficiency, controls the power fluctuation of the light source within ±0.5%, and extends the maintenance cycle of optical components by 2 times. It can be widely applied to next-generation high-power extreme ultraviolet lithography light source systems, meeting the application requirements of semiconductor miniaturization processes.

This invention discloses a design method for parallel current sharing of BOOST multiphase interleaved silicon carbide single transistors. It identifies key parasitic parameters by building a dual-pulse simulation platform, completes device layout in conjunction with the overall system structure, uses PCB symmetry and copper layer stacking to control parasitic parameter consistency, and forms a design closed loop through dual-pulse and steady-state thermal testing. This effectively solves the problem of poor current sharing in parallel silicon carbide single transistors. Furthermore, this method ensures balanced current distribution during switching transients and conduction steady states, eliminates current sharing failures caused by parasitic parameter mismatch, fully utilizes the performance of silicon carbide single transistors without requiring amplification device margins, flexibly adapts to the overall system layout, improves space utilization, optimizes system efficiency, reduces design costs and redundancy, and achieves a reliable, efficient, and highly adaptable design for parallel current sharing of BOOST multiphase interleaved silicon carbide single transistors.

The application provides a low-temperature double-pulse test platform and method, and relates to the technical field of power device testing.The platform comprises a refrigeration compressor, a cooling platform, an enclosure, an air extraction unit, a temperature acquisition unit, a parameter acquisition unit and a control unit.The control unit is used for acquiring surface temperature information of the power device to be tested, platform temperature information of the cooling platform and thermistor parameters under the action of a calibration pulse during the cooling process, determining the corrected equivalent junction temperature parameters of the power device to be tested, and controlling the double-pulse test loop to perform double-pulse testing when the corrected equivalent junction temperature parameters enter a target test temperature window.The method introduces a calibration pulse and thermistor parameters on the basis of a low-temperature environment, corrects and characterizes the actual thermal state of the power device to be tested, and controls the double-pulse testing time in combination with the target test temperature window, so as to improve the accuracy, consistency and repeatability of low-temperature double-pulse testing.

This invention relates to a method and system for identifying reverse recovery conduction paths and predicting dynamic characteristics of SiC MOSFETs, belonging to the field of power semiconductor device testing and reliability analysis. The method includes: Step 1: Constructing a dual-pulse test circuit and acquiring waveform data; Step 2: Preprocessing the data; Step 3: Extracting feature parameters and constructing feature vectors; Step 4: Outputting the conduction path type and device degradation state; Step 5: Based on the conduction path type, combined with the total current decomposition relationship and the dynamic response characteristics of the device under different test conditions, establishing a conduction path decomposition model, and calculating the current proportions of the MOS channel conduction path, body diode conduction path, and Schottky diode conduction path; Step 6: Predicting reverse recovery parameters; Step 7: Assessing device status, predicting remaining lifetime, and assessing failure risk. This invention automates the processing of dual-pulse test data and, for the first time, achieves quantitative identification of conduction paths.