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Technical mapping control method, device and system based on rear-end requirements

A control method and technology, applied in the field of FPGA, can solve problems such as poor mapping results, difficulty in meeting mapping requirements, and inability to meet back-end requirements.

Active Publication Date: 2020-05-12
GOWIN SEMICON CORP LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Practice has found that different user designs and partial netlists often have different mapping requirements, and the same user design and partial netlist also have different mapping requirements on different devices, and the mapping results obtained by current technical mapping methods are difficult to satisfy The mapping requirements of various user designs and local netlists on different devices lead to poor mapping results and technical problems that cannot meet the back-end requirements

Method used

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  • Technical mapping control method, device and system based on rear-end requirements
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  • Technical mapping control method, device and system based on rear-end requirements

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Embodiment 2

[0115] see figure 2 , figure 2 It is a schematic flowchart of another technology mapping control method based on back-end requirements disclosed in the embodiment of the present invention. in, figure 2 The described method can be applied in an EDA development tool, which at least includes a front-end logic synthesis device and a back-end processing device. Such as figure 2 As shown, the technology mapping control method based on back-end requirements may include the following operations:

[0116] 201. The back-end processing device reads the post-synthesis netlist generated by the front-end logic synthesis device.

[0117] 202. The back-end processing device executes a target operation on the read integrated netlist, and obtains an operation result corresponding to the target operation.

[0118] 203. The back-end processing device determines the back-end requirements of the back-end processing device according to the operation result corresponding to the target operat...

Embodiment 3

[0142] see image 3 , image 3 It is a schematic flowchart of another technology mapping control method based on back-end requirements disclosed in the embodiment of the present invention. in, image 3 The described method can be applied in an EDA development tool, which at least includes a front-end logic synthesis device and a back-end processing device. Such as image 3 As shown, the technology mapping control method based on back-end requirements may include the following operations:

[0143] 301. The back-end processing device reads the post-synthesis netlist generated by the front-end logic synthesis device.

[0144] 302. The back-end processing device determines the cumulative interaction parameters between itself and the front-end logic synthesis device, and judges whether the cumulative interaction parameters are greater than or equal to a predetermined interaction parameter threshold. When the judgment result in step 302 is yes, this process can be ended. When t...

Embodiment 4

[0162] The embodiment of the present invention discloses another technology mapping control method based on back-end requirements. The method is applied to the front-end logic synthesis device included in the EDA development tool. The method may include the following operations:

[0163] The front-end logic synthesis device generates a synthesized netlist, wherein the synthesized netlist generated by the front-end logic synthesis device is used to provide the back-end processing device to trigger the back-end processing device to judge the technology mapping in the read synthesized netlist Whether the result matches the pre-determined back-end requirements, and when a mismatch is judged, generate technology mapping guidance information and feed it back to the front-end logic synthesis device;

[0164] The front-end logic synthesis device detects whether the technology mapping guidance information fed back by the back-end processing device is received; when the detection result ...

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Abstract

The invention discloses a technical mapping control method, device and system based on rear-end requirements. The method comprises the steps that a rear-end processing device reads a comprehensive rear netlist generated by a front-end logic comprehensive device and judges whether a technical mapping result in the comprehensive rear netlist is matched with the rear-end requirements or not; when thejudgment result is no, technical mapping guide information is generated and fed back to the front-end logic synthesis device; when the technical mapping guide information fed back by the back-end processing device is received, the front-end logic comprehensive device executes local mapping operation on logic resources in user design according to the technical mapping guide information to obtain anew technical mapping result and updates the new technical mapping result to the comprehensive rear netlist to generate a new comprehensive rear netlist, and the comprehensive rear netlist generatedby the front-end logic comprehensive device is used for being provided for the rear-end processing device. Visibly, by implementing the method and the device, accurate guide information can be provided for technical mapping according to the back-end requirements, the quality of the mapping result is improved, and the matching degree of the mapping result and the back-end requirements can be further improved.

Description

technical field [0001] The present invention relates to the field of FPGA technology, in particular to a technology mapping control method, device and system based on back-end requirements. Background technique [0002] The FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) design process is a process of developing FPGA chips using EDA (Electronics Design Automation, electronic design automation) development software and programming tools. The development process of EDA development software mainly includes the front-end logic synthesis process and the back-end layout and routing, timing analysis and power consumption analysis and other processes. Among them, technology mapping is an important part of the logic synthesis process. The specific process is to map the logic resources in the user design into a logic lookup table through a general mapping algorithm and output it to the post-synthesis netlist. [0003] Practice has found that different user designs...

Claims

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Application Information

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IPC IPC(8): G06F30/327G06F30/343
Inventor 刘奎王宁王维王勇麟宋宁刘建华
Owner GOWIN SEMICON CORP LTD
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