Processing method of ROM (Read-Only-Memory) technology mapping

Abstract

The invention provides a processing method of ROM (Read-Only-Memory) technology mapping. The method comprises the following steps: identifying the basic structure of an ROM from source description in which a hardware description language is taken as a format; constructing a control data flow graph node of the ROM according to the identified basic structure of the ROM; mapping the ROM to a target ROM unit in a mapping library according to the constructed control data flow graph node of the ROM. According to the method, mapping from behavioral level ROM description to an ROM target process library in FPGA (Field-Programmable Gate Array) RTL (Register-Transfer-Level) synthesis is realized through ROM identification and mapping, the processed ROM is implemented on an ROM macro unit of an FPGA, and the same effect as a Synplify synthesis tool is achieved.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a processing method for ROM process mapping in FPGA RTL synthesis. Background technique [0002] FPGA (Field-Programmable Gate Array), that is, field programmable gate array, is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. At present, the EDA development technology of FPGA (Field Programmable Gate Arrays) is mainly controlled by several major FPGA and EDA manufacturers, such as Xilinx, Altera, Synopsis, etc. The domestic technology development is still in the stage of following and imitating. Among them, RTL (Register-Transfer-Level) synthesis is an important part of...

AI Technical Summary

Problems solved by technology

[0005] The synthesis of FPGA on-chip ROM has been widely integrated in FPGA RTL synthesis tools, such as Synopsis’s Synplify and Xilinx’s XST, etc., but the relevant documents are only user-level manuals, which focus on introducing different RTL-level descriptions of ROMs and ROM types in target FPGAs The mapping relationship, the specific comprehensive technical implementation details are not disclosed

In practice, there is no public technology to solve this problem

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