A process layer management and display method supporting multi-
chip stacking design comprises the following steps: analyzing a
layout file, generating a process layer
list and a
core particle list of all core particles, and distributing a corresponding shadow layer for each
core particle; the shadow layer comprises a layer number and a layer name of the process layer, and a definition for controlling visible, selectable and color display of the core particles or the process layer; searching all core particles containing corresponding process
layers from the
core particle list and the process layer list according to input layer numbers and layer names, and performing highlight display; when the editing area is switched, the process layer of the target core particle is set to be in an
active state in the process layer list; and storing the editing operation data of the process layer in the current
active state into an independent
layout file. An independent shadow layer is bound for each core particle, and the number and the name of the original process layer are reused, so that the correct editing behavior is ensured; the core particles and all process
layers in the core particles are managed and displayed through coarse and fine
granularity, so that the management and display problems of cross
layers among different processes are solved.