This application belongs to the field of
direct memory access control technology, specifically providing a
direct memory access control method and
system to reduce CPU interrupt handling load. The method mainly includes: acquiring the device
list and historical transfer data of DMA devices, and establishing an initialization parameter set; performing
feature extraction and classification sorting on real-time arriving
direct memory access requests according to the initialization parameter set to obtain an ordered request group sequence; performing address continuity analysis and dynamic aggregation
processing on the ordered request group sequence to obtain a
transfer parameter set; and performing transfer progress prediction and interrupt sharing management based on the
transfer parameter set to obtain an interrupt trigger
control signal. This application effectively solves the problem in the prior art where, with the increase in the number of peripherals and the growth in transmission demand, a large number of independent requests directly lead to a surge in CPU interrupt handling load, ultimately significantly restricting data transfer
throughput. It significantly reduces the CPU interrupt handling load, reduces its
resource consumption, and makes the data transfer process more efficient.