954 results about "Graph design" patented technology

A three-dimensional point cloud semantic segmentation method based on graph convolution and a grouping vector attention mechanism adopts a network structure of a U-Net style, feature extraction and propagation are performed on point cloud through multi-level feature coding and decoding, each level firstly centralizes and standardizes local neighborhood features through a geometric affine module, and then the local neighborhood features are subjected to feature extraction and propagation; the capturing capability of the model on the diversity of the local region is enhanced; secondly, constructing a local neighborhood graph, and designing an asymmetric edge feature learning function to extract local topological information; deep edge features are further extracted in combination with a residual network; and finally, selectively fusing local features and global context information under the condition of low parameter quantity by using a grouping vector attention mechanism, and performing cross-level feature interpolation up-sampling to an original scale to complete point cloud segmentation. The method can significantly improve the point cloud segmentation precision, and is suitable for the perception of a mobile robot and other devices carrying a three-dimensional sensor on a complex scene.

The invention relates to a multi-modal data generalization learning method and system based on causal invariant transformation. The method comprises the following steps: acquiring multi-modal data to construct a causal graph; designing causal invariant transformation to simulate a causal relationship, keeping causal features in the causal relationship unchanged, changing non-causal features, and generating a new training sample; fusing information of different modes; and constructing a self-supervised learning framework, predicting labels of the node pairs as pre-training tasks, and learning feature representation and causal structures of the multi-modal data. A causal graph is constructed and analyzed, causal invariant transformation is designed to simulate a causal relationship and generate a new training sample, and the model can learn feature representation consistent with a causal structure, so that stable performance is kept on different distributed data; according to the method, a self-supervised learning framework is constructed, extra labeling information is not needed, data representation and causal structures are learned by predicting labels of node pairs as pre-training tasks, and the generalization ability of the model can be effectively improved.

The invention belongs to an aircraft wire harness design technology, and relates to a digital and automatic collaborative design simulation method for aircraft wire harnesses based on Capal and CATIA. According to the method, an existing boundary data model is utilized, electrical parts are installed on CATIA software, and wiring harness arrangement environment conditions are created; creating a three-dimensional wire harness model in the CATIA software; establishing a Capal graphic symbol library and a wire harness part library; creating an aircraft electrical wiring diagram on the Capital software by using the graphic symbol library and the wiring harness part library file; in combination with a CATIA three-dimensional wiring harness model, interactive design is carried out with flight Capital software, and an aircraft two-dimensional topological graph is formed; the sectional area of the wire harness is automatically calculated through CATIA software, and an aircraft simulation three-dimensional wire harness is formed; and combining the aircraft simulation three-dimensional wiring harness with the aircraft topological graph and the aircraft wiring harness two-dimensional graph design to form an aircraft two-dimensional wiring harness chart diagram. According to the invention, database management informatization, three-dimensional wiring harness design digitalization, two-dimensional electrical system principle design and three-dimensional electrical wiring harness model interaction design automation are realized.

The invention relates to the technical field of CAD drawing optimization, and discloses a CAD drawing optimization method based on parameterized design. The method comprises the steps that a design constraint condition set is received, and geometric constraint parameters and engineering constraint parameters in the design constraint condition set are extracted; generating an initial geometric topological structure according to the geometric constraint parameters, and performing parameterized mapping on the structure in combination with the engineering constraint parameters to form a parameterized geometric model; identifying key feature nodes in the model, dynamically associating the key feature nodes with engineering constraint parameters, and constructing a parameter-driven relation network; and iteratively optimizing the parameterized geometric model through the network to generate an optimized geometric model meeting a design constraint condition set. According to the method, close association of geometry and engineering constraints is achieved, repeated design modification is reduced, efficiency and accuracy are improved, the design standardization degree can be improved, collaborative design is facilitated, and the method is suitable for CAD drawing design of complex products.

The invention relates to an application method of a GPU (Graphics Processing Unit) in design rule inspection in the field of integrated circuits, in particular to a layout design rule inspection method, system and equipment, a medium and a product. The layout design rule checking method comprises the following steps: inputting initial layout data, analyzing a design rule checking task to be executed, and marking the priority and complexity level of the task; the method comprises the following steps: dividing layout data into a plurality of data blocks according to regions on the basis of regional characteristics of the layout data, distributing tasks and corresponding data blocks to a GPU computing core according to task priorities and complexity levels, and distributing new data blocks according to the overall load condition of the GPU computing core after the GPU computing core completes data block processing, and repeating the steps until all tasks are executed, and outputting a layout design rule check result. The system, the computer equipment, the computer readable storage medium and the computer program product have the same beneficial effects as the layout design rule checking method.

The invention provides a PCELL layout design optimization method and device, a medium and equipment, and is applied to the technical field of chip design. Flexible layout drawing is carried out by acquiring the PCELL containing the process parameters and the graph adjustable parameters, so that the layout structure parameters of the current PCELL are obtained. A three-dimensional device simulation model is constructed by using the parameters, and a simulation compact model is created by using an artificial neural network algorithm to describe the electrical behavior of the device. And verifying the electrical performance trend of the three-dimensional device simulation model by using the PCELL and the simulation compact model. And when the verification is passed, further verifying whether the module test circuit meets a preset PPA index. And if yes, fixing the structural parameters of the current PCELL layout. According to the method, process and design requirements are integrated through a construction and parameterization method, and simulation and verification of closed-loop feedback are utilized, so that the design precision and the process maturity are improved, the development period is shortened, and the reliability and efficiency of the process are enhanced.

The invention discloses an engineering drawing automatic labeling method and device based on feature direction matching and a storage medium, and belongs to the technical field of size labeling, and the method comprises the steps: obtaining all parts of an entity three-dimensional model and features corresponding to all the parts according to the entity three-dimensional model corresponding to an engineering drawing; obtaining the direction of each feature in the three-dimensional coordinate system; obtaining each view of the entity three-dimensional model and the direction of each view in a three-dimensional coordinate system; based on the direction of the features and the direction of the view, matching each feature with a preferred view suitable for size display of the feature, and performing size marking on each geometric edge of the feature on the matched view; and obtaining uniformly distributed size marking text positions. According to the method, the corresponding relation between the part features in the three-dimensional space is converted into the two-dimensional engineering drawing, the correlation between the size and the view can be rapidly calculated in the engineering drawing, the proper position of size marking can be automatically calculated, and the engineering drawing design efficiency is greatly improved.

Systems and methods for orchestrating events in distributed DevOps apparatus leveraging generative AI are disclosed to automate and streamline software development and deployment in distributed DevOps environments using Generative Adversarial Networks (GANs) and other AI techniques. The method involves interpreting UML diagrams, design documents, or the like with generative AI and computer vision to create DevOps tasks, integrating with various DevOps tools for task management, and deploying generated rules for automated event execution. Metadata is generated and processed in order to facilitate AI analysis. The systems and methods reduce manual intervention, increase efficiency, and improve accuracy, scalability, security, and compliance in DevOps workflows.

The invention discloses an integrated circuit layout design teaching assistance method, and relates to the field of integrated circuits, and the method comprises the steps: receiving a circuit diagram creation instruction, and generating a circuit diagram drawing interface according to the circuit diagram creation instruction; identifying types and connection relations of circuit devices in the circuit diagram drawing interface; according to the identified circuit device type and the connection relation, generating a corresponding circuit schematic diagram data structure by adopting a graph neural network GNN algorithm based on message passing; converting the schematic circuit diagram data structure into a layout data structure; the layout data structure comprises geometric parameters and layout position data of layout elements; and according to the layout data structure, generating a circuit layout by using a reinforcement learning algorithm based on a graph neural network. In view of low integrated circuit layout design efficiency in the prior art, the design efficiency is improved by constructing a multi-objective optimized Markov decision process, utilizing deep learning and reinforcement learning algorithms and the like.

The invention relates to the field of intelligent architecture diagram design rationality judgment, and discloses an architecture diagram rationality analysis and judgment method based on multi-modal feature fusion, and the method comprises the steps: obtaining a to-be-analyzed architecture diagram; identifying and extracting annotated text information in the architecture graph, and recording the annotated text information; identifying and acquiring a region-of-interest feature map set of the image elements through an R-CNN model, and recording the region-of-interest feature map set; establishing a position and logic information corresponding relation between OCR module text information and R-CNN model image elements, and generating an extended text description; performing word segmentation processing and semantic coding on the expanded architecture image text to obtain a word granularity feature vector set; performing semantic coding to obtain a word granularity feature vector set; generating comprehensive feature vectors of the same dimension; and calculating a semantic matching coefficient, and judging whether the design of the to-be-analyzed architecture graph meets the rationality requirement of overall planning or not. Whether the design and the function of the architecture diagram meet the overall planning requirement can be effectively evaluated, and the accuracy and the efficiency of analysis and review are improved.

The invention relates to the technical field of integrated circuits, and discloses an integrated circuit through hole resistance extraction method and device, a storage medium and electronic equipment. The method for extracting the through hole resistance of the integrated circuit comprises the following steps: reading layout design related data of the integrated circuit; determining physical level information related to a metal layer and a through hole in the integrated circuit; constructing a connected network diagram of each physical hierarchy based on the physical hierarchy information; determining communication information and electrical affiliation information of the through holes based on the communication network diagram; the through holes are combined through a set scanning line algorithm to obtain combined through holes, and the combined through holes need to meet set through hole combination conditions; and calculating an equivalent resistance value of the combined through holes based on the resistance values of the combined through holes. According to the technical scheme, the number of post-simulation parameters can be reduced, the simulation time is shortened, meanwhile, it is ensured that the combined resistance network topology is consistent with a physical circuit, and the simulation precision is high.

The invention relates to the technical field of layout design, and discloses a semiconductor device layout fusion method, device, equipment and medium, and the method comprises the steps: obtaining a first simulation project file and a second simulation project file, determining a target layer layout based on the preset level information of the two layers of layouts, and carrying out the fusion of the two layers of layouts according to a preset incidence relation, respectively obtaining the position information of the mapped target graphic element and the position information of the mapped third graphic element from the position information of the target graphic element and the position information of the third graphic element; and determining layout position information of the third layer layout in the target layer layout according to the mapped position information of the target graphic element and the mapped position information of the third graphic element, and importing the third layer layout into the target layer layout according to the layout position information. Accurate superposition of layout elements of different layers is ensured, and the problems of staggering, dislocation and the like are solved.

The invention relates to the technical field of layout design, and particularly provides a PCB layout design verification method, system and device and a medium, and the method comprises the steps: extracting a design intention from a design demand text through a natural language processing technology; querying design constraint parameters from a pre-constructed knowledge graph based on the design intention; generating a dynamic verification rule according to the design constraint parameter; and verifying the design parameters in the PCB layout by using a rule engine and applying the dynamic verification rule, and outputting a verification result. According to the invention, the verification efficiency is improved, and the rework rate caused by constraint deficiency is reduced.

The invention discloses a thinking data-based large model reasoning ability evaluation and analysis method and device. According to the method, a data flow diagram is constructed through a variable use-definition chain during running of a specific language LMCL in the dynamic monitoring field, logic variable LVAR nodes are extracted, redundant edges are eliminated, and a thinking map with a direct dependency relationship is generated. Based on the thinking map, a five-dimensional evaluation system including reasoning efficiency, key node recognition capability, reasoning generality, multi-path reliability and accumulative hierarchical reasoning is designed, and an internal mechanism of a model reasoning process is quantitatively analyzed. A semantic rule is extracted through a frequent mode of mining successful and failed thinking data, reasoning path probability distribution is integrated in combination with a path aggregation strategy, an interpretable cue word optimization strategy is generated, and a large model reasoning process is dynamically injected. Through the rule guidance and path equalization strategy, the model reasoning accuracy is improved, and the problems of thinking data isomerism, single evaluation and black box enhancement in the traditional technology are solved.

The invention provides a preparation method and device of a three-dimensional layered puzzle, electronic equipment and a storage medium, and the method comprises the following steps: obtaining a two-dimensional design image, and carrying out the preprocessing of the two-dimensional design image; performing stereoscopic enhancement processing on the preprocessed two-dimensional design image to generate a preliminary three-dimensional image; processing the preliminary three-dimensional image to generate a three-dimensional model; layering the three-dimensional model to form a plurality of required target layers; performing arrangement layout on the plurality of target layers, and outputting a drawing of the plurality of target layers including the optimal arrangement layout; and a layered cutting file is generated according to the drawing, the manufacturing equipment receives the layered cutting file, and puzzle layer modules are manufactured. The method has the beneficial effects that the whole preparation process of the jigsaw type toy is automatic, manual intervention is not needed from two-dimensional drawing to layered jigsaw design, the limitation of dependence on a designer in the prior art is broken through, output files are directly in butt joint with production equipment, industrial practicability is achieved, and the manufacturing cost is reduced.

The invention discloses a multi-agent system for knowledge-driven automatic software architecture design, and belongs to the technical field of computer aided design, and the multi-agent system comprises an analysis agent, a modeling agent, a design agent and an evaluation agent which are constructed based on a large language model, the analysis agent is used for extracting, screening and classifying requirements which influence the software architecture design from a software requirement specification and generating a requirement document; the modeling agent is used for generating a software architecture view according to a demand document and an external knowledge base; the design agent is used for generating a software architecture document according to the demand document and the software architecture view; and the evaluation agent is used for evaluating and analyzing the software architecture according to the demand document, the software architecture view and the software architecture document to generate an evaluation and analysis report. According to the method, through cooperation and interaction between the intelligent agents and prompt of external knowledge, the reliability, practicability and creativity of software architecture design can be effectively enhanced.

1. The name of this design product: Graphical user interface for patented technology mining of electronic devices. 2. Purpose of this design product: applied to an electronic device. 3. The key design point of this appearance design product lies in the graphical user interface. 4. The picture or photo that best illustrates the key points of the design: Main view of Design 1. 5. Designate Design 1 as the base design. 6. Purpose of graphical user interface: used for technical mining of patents. 7. Human-computer interaction mode of the graphical user interface: When entering the solution interface, the Design 1 main view is presented. Enter the patent technology keyword in the edit input box of the Design 1 main view to present the Design 1 interface change state diagram 1. Click the Recommended Technical Problem button in the Design 1 interface change state diagram 1 to present the Design 1 interface change state diagram 2. Click the Technical Solution Mining button in the Design 1 interface change state diagram 2 to present the Design 1 interface change state diagram 3. Click the Initial Technical Inspiration button in the Design 1 interface change state diagram 3 to present the Design 1 interface change state diagram 4. The steps of the Design 2 main view - Design 2 interface change state diagram 3 are the same as those of the Design 1 main view - Design 1 interface change state diagram 3. Click the Technical Inspiration Draft Box button in the Design 2 interface change state diagram 3 to present the Design 2 interface change state diagram 4. The steps of the Design 3 main view - Design 3 interface change state diagram 3 are the same as those of the Design 1 main view - Design 1 interface change state diagram 3. Click the Similar Patents button in the Design 3 interface change state diagram to present the Design 4 interface change state diagram 4.

The invention discloses an abnormal traffic flow detection method and system based on a dynamic graph, and is applied to the field of abnormal traffic flow detection. The method comprises the following steps: dividing a city into a plurality of sub-regions through city road network data, and obtaining vehicle trajectory data to construct a traffic flow tensor; constructing an approximate graph based on the traffic flow tensor and performing data enhancement to generate a local view and a global view of the traffic flow tensor; designing a comparative learning model with a time graph encoder to perform joint training on the multi-view data, and capturing space-time dependency features; and acquiring a real-time traffic flow embedding vector by adopting a sliding window, identifying an abnormal traffic mode through a local abnormal factor algorithm, and finally realizing the positioning of an urban abnormal traffic area. According to the method, through fusion of the time graph encoder and comparative learning, the accuracy of traffic anomaly detection in a complex road network environment is effectively improved, and reliable technical support is provided for urban traffic intelligent management.

The invention discloses an intelligent contract vulnerability detection method based on a multi-level data dependence heterogeneous graph, and belongs to the technical field of intelligent contract security. Intelligent contract byte codes are used as input, contract byte codes are converted into operation codes, and a control-data heterogeneous graph with basic blocks as nodes is constructed; designing an in-block data dependency sub-graph, and forming multi-level data dependency with the inter-block data stream; based on the generated control-data heterogeneous graph, a feature weighted relation graph convolutional network is provided, and control flow and data flow feature weights are dynamically adjusted and optimized by using node static attributes such as dominating tree depth and the like, so that multi-modal semantic efficient aggregation is realized. According to the method, for the contract without a public source code on the block chain, vulnerability detection only for the bytecode of the intelligent contract is realized, and high detection efficiency can be achieved under the condition that the detection accuracy is guaranteed.

The invention provides a DCS electrical isolation device set diagram design method and device, and the method comprises the steps: obtaining an electrical isolation signal list, and constructing an electrical isolation signal configuration table according to all signals of various types in the electrical isolation signal list; defining macro elements of the electrical isolation device based on the signal information and a standard drawing template to obtain a plurality of graph macros; defining a break point name according to the path of the target signal in the electrical isolation signal configuration table; and designing an electrical isolation device complete set diagram based on the electrical isolation signal configuration table, the plurality of diagram macros and the interruption point names by utilizing preset electrical design software. According to the method, the electrical isolation signal configuration table, the electrical isolation graph macro and the interruption point are defined in detail by adopting a parameterization design method, and automatic drawing is realized. And by standardizing the design sequence, the risk of human errors is reduced. And the design method and steps are kept consistent, so that the consistency of design quality is ensured, and the standardization and specialty of the overall design are improved.

According to the OPC detection and early warning method for the layout graph exceeding the process capability problem, when DRC check is completed and an error is reported, the following detection is carried out: a graph at an error reporting position of design rule check is marked and is used as a graph with a large risk class; and performing regular classification on the risk large-class graphs according to the graph features to divide the risk large-class graphs into first-class graphs and second-class graphs. The first-class graphs are high-risk graphs exceeding the process capability, and when the first-class graphs exist, the first-class graphs are fed back to the layout design end. The second type of graphs are potential risk graphs, when the second type of graphs exist, second screening is carried out on the second type of graphs, and the second screening comprises the step of carrying out local OPC correction to obtain the first layout layer. And adopting an OPC AEI model to carry out local OPC to judge whether a defect risk graph exists or not, and feeding back the defect risk graph to a layout design end when the defect risk graph exists. According to the method and the device, the defect problem caused by the problem layout graph exceeding the process capability can be quickly and comprehensively screened, so that the publishing efficiency can be improved.

The invention provides an LVS rule detection method, apparatus and device, and a storage medium. The method comprises the steps of obtaining a to-be-detected layout netlist and a schematic diagram netlist; performing structured text representation on the to-be-detected layout netlist and the schematic diagram netlist, and performing cue word optimization operation to obtain target cue word information; searching an LVS rule related to the layout netlist to be detected and the schematic diagram netlist in a rule database according to the target cue word; and inputting the to-be-detected layout netlist, the schematic diagram netlist and the LVS rule into an LVS rule verification model to determine the consistency of the to-be-detected layout netlist and the schematic diagram netlist. By performing cue word optimization operation on the text representation of the layout netlist and the schematic diagram netlist, the pre-trained large language model can be guided to better understand the semantics of the design text, so that the performance of the LVS verification model is improved. The optimized cue word information can enhance the recognition capability of the model to the design rule, and ensures the adaptability of the model to the new layout design.

1. Name of the design product: Graphical user interface for glaucoma gait feature setting of an electronic device. 2. Use of the design product: An electronic device. 3. Design key points of the design product: Lies in the graphical user interface. 4. Picture or photo that best shows the design key points: The front view of Design 1. 5. The electronic device is of a conventional design, and the rear view, left view, right view, top view, and bottom view are omitted. 6. Design 1 is designated as the basic design. 7. Use of the graphical user interface: The front view of Design 1 is the operation interface for logging in to the glaucoma gait feature construction system. The user clicks "Glaucoma-1" in the front view of Design 1 to enter Figure 1 of the interface state change of Design 1. The user clicks "01-1" in Figure 1 of the interface state change of Design 1 to enter Figure 2 of the interface state change of Design 1. The user clicks "celling light" in Figure 2 of the interface state change of Design 1 to enter Figure 3 of the interface state change; The front view of Design 2 is the operation interface for logging in to the glaucoma gait feature construction system. The user clicks "Glaucoma-1" in the front view of Design 2 to enter Figure 1 of the interface state change of Design 2. The user clicks "01-1" in Figure 1 of the interface state change of Design 2 to enter Figure 2 of the interface state change of Design 2. The user slides the left menu in Figure 2 of the interface state change of Design 2 and then clicks "Targets" to enter Figure 3 of the interface state change of Design 2; The user clicks "01Chest" in Figure 3 of the interface state change of Design 2 to enter Figure 4 of the interface state change of Design 2; The front view of Design 3 is the operation interface for logging in to the glaucoma gait feature construction system. The user clicks "Glaucoma-1" in the front view of Design 3 to enter Figure 1 of the interface state change of Design 3. The user clicks "01-1" in Figure 1 of the interface state change of Design 3 to enter Figure 2 of the interface state change of Design 3. The user slides the left menu in Figure 2 of the interface state change of Design 3 and then clicks "shengao" to enter Figure 3 of the interface state change of Design 3; The front view of Design 4 is the operation interface for logging in to the glaucoma gait feature construction system. The user clicks "Glaucoma-1" in the front view of Design 4 to enter Figure 1 of the interface state change of Design 4. The user clicks "01-1" in Figure 1 of the interface state change of Design 4 to enter Figure 2 of the interface state change of Design 4. The user slides the left menu in Figure 2 of the interface state change of Design 4 and then clicks "f666d6de-10c9-4c0f-8b" to enter Figure 3 of the interface state change of Design 2. 8. Other situations that need to be explained: Other explanations: The gray part in the picture is variable content. It can display different contents according to the user's personalized operations.

The invention discloses a multi-dimensional test case generation method and device, and relates to the technical field of test case generation, and the method comprises the steps: building a unified causal diagram model through analyzing a schematic circuit diagram, designing a constraint document, simulating data and other multi-source inputs according to the verification demands of a complex electronic system, and automatically generating a multi-dimensional test case, the technical problems that in related technologies, model type dependency is high, natural language constraint analysis operation is lacked, schematic diagrams, design specifications, signal integrity simulation and other data generated in the design stage exist in an isolated mode, overrun scenes are ignored, and the scene coverage local limit is high are solved, and the purpose that multi-source design data are fused, so that the design efficiency is improved is achieved. The unified causal graph model is constructed, and the complete expression of the design intention and the dominance of the implicit knowledge are realized, so that the technical effects of remarkably improving the coverage range of the test scene and the utilization efficiency of the test resources are achieved.

The invention provides an area generation method and device in a multi-layer map, electronic equipment and a storage medium, and relates to the technical field of map design, and the method comprises the steps: determining the number of layers of the map and the number of areas in each layer of the map; generating a plurality of polygonal areas with the same number as the areas in each layer of map; for two adjacent layers of maps, determining an affiliation relationship between the polygonal area in the lower layer of map and the polygonal area in the upper layer of map; and in the affiliation relationship, adjusting the area shape of the polygonal area in the upper map by using the side information of the polygonal area in the lower map until the area shapes of all the polygonal areas in the upper map are adjusted. According to the method, unreasonable region boundary division in each layer of map can be avoided, and accurate region division of each layer of map is ensured. According to the method, the requirements on the performance and the storage space of the computing equipment can be remarkably reduced through edge-level data processing.

The embodiment of the invention discloses a digital delivery method based on a gas overground pipeline, and the method comprises the steps: collecting the basic information of a to-be-delivered project, and generating a gas planar graph according to the basic information; the method comprises the following steps: designing a VR scanning scheme, scanning a space environment where a to-be-delivered project is located according to the VR scanning scheme to obtain a 720-degree space three-dimensional model, and processing data in the 720-degree space three-dimensional model to obtain a three-dimensional high-precision model; uploading the gas planar graph and the three-dimensional high-precision model to a cloud platform; the cloud platform adds labels to important information on the three-dimensional high-precision model and the gas planar graph, wherein the important information comprises information of directions of a gas vertical pipe, a pressure regulating cabinet, a gas meter, an electromagnetic stop valve, gas utilization equipment and a gas pipeline; and completing delivery through the cloud platform. According to the method, the gas facility safety operation and maintenance guarantee capability of the gas overground pipeline is improved, and the data delivery accuracy of the gas overground pipeline is improved.

The invention discloses a layout parameterization hierarchical parallel mesh generation method based on Net. The method comprises the following steps: inputting a layout design file, analyzing hierarchical structure identification ports, generating a port set P and creating an accessed port set V (initial V =); a graph G = (VG, EG) is constructed, VG comprises key vertexes or geometric centers of ports and conductor fragments, an electrically independent Net is generated through traversal of a breadth-first search algorithm or a depth-first search algorithm, and iteration is performed until V is completely equal to P; configuring independent subdivision parameters such as a grid size and a grid algorithm for each Net; net is used as an independent task, grids are divided through parallel computing frameworks such as multithreading, and a complete grid file for subsequent simulation is generated after merging. According to the method, Net automatic identification is realized through graph theory analysis; different Net precision requirements are adapted by differential subdivision parameters, so that waste of computing resources is avoided; through parallel processing, the time consumption of layout grid division is shortened to the time consumption of processing the maximum Net, and the efficiency and the flexibility of simulation pre-processing are remarkably improved.

The invention discloses a modeling method for each stage of a bridge based on meta-components. The method comprises the following steps: constructing a bridge full-life-cycle digital representation description rule based on the meta-components; developing a meta-component model in a construction drawing design stage; performing simplification and recombination on the basis of the meta-component model of the construction drawing design stage, and generating models of a preliminary design stage and a planning stage; carrying out refined expansion on the basis of the meta-component model of the construction drawing design stage, and generating models of a construction stage and an operation stage; and establishing a full-cycle model management system. According to the modeling method for each stage of the bridge based on the meta-components, the full-life-cycle digital representation description rule is constructed, the meta-component models in the construction drawing design stage are developed, effective conversion of models in different stages is achieved, and a full-cycle model management system is established; the problems of low efficiency and the like caused by incomplete information transmission and repeated model creation in the prior art are solved.

The invention aims to provide a Bayesian optimization-based EDA (Electronic Design Automation) tool parameter automatic tuning method and system. The method comprises the following steps of: setting a process library file, a hardware description language code of chip design and a constraint file, and configuring a parameter space formed by EDA tool parameters; inputting the process library file, the hardware description language code of the chip design, the constraint file and the parameter space into DGPSPMBO; and the DGPSPMBO outputs a chip layout design according to a diversity-guided multi-target Bayesian optimization framework. According to the method, important parameters are selected to ensure that optimization is concentrated on the most effective parameter dimension, and the search accuracy is improved. And meanwhile, a parallel optimization strategy considering parameter space and PPA index diversity is introduced, and exploration is guided by utilizing a batch selection mechanism and combining a hyper-volume improvement index, so that exploration is more sufficient, and a plurality of EDA tool parameter combinations capable of realizing high-quality chip design can be quickly and accurately found.

The invention discloses a malicious code control flow feature extraction method based on a graph neural network. The method comprises the following steps: constructing a control flow graph, a data flow graph and a function call graph; designing a drawing neural network architecture; training a graph-level classifier; performing graph interpretation by using a GNNExplainer algorithm, attention mechanism analysis and a gradient analysis method; converting the extracted control flow mode into a structured detection signature, and mapping the structured detection signature to an original binary code; and integrating with a static analysis tool through a standardized interface. The invention further discloses a malicious code control flow feature extraction system based on the graph neural network. Multi-level graph structure representation is constructed, important information such as a control flow structure and a data dependency relationship is fully reserved, the deep structure similarity of malicious codes can be recognized, the deformation resistance is higher, and therefore the malicious code detection precision is improved; according to the method, key sub-graphs can be recognized, graph structure features are converted into detection rules, then the detection rules are integrated with existing static analysis tools, and practicability is improved.