Auxiliary chip design method for reducing simulation time

Abstract

The invention discloses an auxiliary chip design method for reducing simulation time. The method comprises the following steps: firstly, establishing a standard element library; establishing a reference model of the analog integrated circuit according to function classification, wherein the reference model comprises element library information of automatic calling and combined connection, a parameter filling space and a part of blank modules needing to be manually designed; selecting a reference model in a development tool according to required functions, filling in parameters, generating a schematic diagram top layer circuit, each module sub-circuit and a form required by module verification, and importing the schematic diagram top layer circuit, each module sub-circuit and the form intoa schematic diagram editor to complete schematic diagram design; and finally, importing a layout design tool, calling the corresponding layout and drawing layout in the standard element library, and verifying, integrating and completely drawing. By applying the method provided by the invention, the consumed time caused by layout rearrangement due to schematic diagram adjustment can be reduced, meanwhile, the simulation time required by most module function verification is also reduced, and the chip design speed is greatly increased.

Description

technical field [0001] The invention relates to a semiconductor chip design method, in particular to an auxiliary chip design method for reducing simulation time in the design of an analog integrated circuit. Background technique [0002] like figure 1 As shown in the figure, in the current design of analog circuit chips, each functional module is drawn separately, and finally the wiring is placed uniformly to form a complete chip. The principle design part often creates a new circuit structure or modifies part of the parameters of the module due to the actual design requirements; The layout part needs to make the corresponding actual layout circuit according to the modification of the principle part. [0003] The parameters modified due to the schematic diagram part vary from person to person due to the personal experience of the principle designer. For example, in order to reduce the current of a branch in the circuit, the resistance of the branch can be increased, or th...

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Problems solved by technology

[0004] In order to overcome the deficiencies of the above-mentioned prior art, the object of the present invention is to propose an auxiliary chip design method that reduces simulation time, and solve the problems of difficult adjustment of schematic diagram and layout and long simulation time in chip design

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