MOS transistor drain electrode control transmission type multi-system and decimal bit weight multiplier

A MOS tube and multiplier technology, applied in the computer field, can solve the problems of slow development and achieve the effect of effective hardware support

Pending Publication Date: 2020-09-01
胡五生
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] So far all computers and their related digital systems are binary. Although multi-valued computing has many advantages, it develops very slowly because there is no key hardware to support multi-valued computing. It can be said that multi-valued computers, especially decimal The realization of computer is almost zero, in view of this situation, the present invention proposes a kind of simple and effective multi-value calculation implementation circuit, especially the effective method of ten-value calculation and realizes multi-value, especially ten-value addition and subtraction with binary hardware , multiplication, division arithmetic operations and the key circuits of logic operations, which are called "quantization logic" and their circuits

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  • MOS transistor drain electrode control transmission type multi-system and decimal bit weight multiplier
  • MOS transistor drain electrode control transmission type multi-system and decimal bit weight multiplier
  • MOS transistor drain electrode control transmission type multi-system and decimal bit weight multiplier

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Embodiment Construction

[0119] Reference figure 2 (1), 2(2), 2(3), using two patent applications 201711119713.x quantized logic multi-ary arithmetic operator to assign the unit circuit described in claim 3 in the fractal integrated unit circuit to form two MOS tube drain control module, multiply 0 module, multiply 1 module. Multiply 0 module press figure 2 (1) The method and figure 1 (1) In the multiplication table, the input and output bit weight information is correspondingly connected to the input and output bit weight bus. Multiply 1 module according to figure 2 (2) The method and figure 1 (1) In the multiplication table, the input and output bit weight information is correspondingly connected to the input and output bit weight bus. Finally follow figure 2 The method (3) connects the input and output buses of the multiply O module and the multiply 1 module according to the corresponding line numbers as the bit weight input and output of the multiplier, which is a binary drain control bit weigh...

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Abstract

The invention discloses a one-bit multi-valued digital multiplier (MOS transistor drain control transmission type multi-system and decimal bit weight multiplier) composed of MOS transistors. The one-bit multi-valued digital multiplier is composed of multiple-valued multiplication modules in different forms. The multi-valued multiplication module is provided with a 0 multiplying module, a 1 multiplying module, a 2 multiplying module,..., and an N multiplying module; the module is formed by combining and connecting arithmetic units which are connected in different modes. The unit is formed by permutation and combination of units according to the claim 3 of the patent application 20171111971. X 'a multi-system arithmetic operator of quantitative logic assignment fractal integrated unit circuit '. Drain electrodes of MOS tubes of all units are connected together to serve as a control end and are connected with a numerical value end of one set of bit weight input, grid electrodes of all theunits in the module serve as another set of bit weight data input end, and the formed module is called a leakage control multiplication operation module. The module outputs are divided into two groups, one group is standard output, and the carry systems of the selected circuits are different.

Description

Technical field [0001] The present invention relates to the field of computer technology, in particular to one of the basic hardware for realizing multi-value computers "MOS tube drain control transmission type multi-system and decimal place weight multiplier" [0002] technical background [0003] So far all computers and their related digital systems are binary. Although multi-value computing has many advantages, it does not have the key hardware to support multi-value operations, so its development is extremely slow. It can be said that multi-value computers, especially decimal systems. The realization of the computer is almost zero. In view of this situation, the present invention proposes a simple and effective multi-value calculation circuit, especially an effective method for calculating the ten value, and the use of binary hardware to realize the addition and subtraction of multiple values, especially the ten value. The arithmetic operation of multiplication, division and t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/52
CPCG06F7/52
Inventor 胡五生
Owner 胡五生
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