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Method for dividing cycle task by means of software and hardware and device thereof

A technology of hardware and software division and task, applied in the direction of multi-programming device, resource allocation, etc., can solve the problems of increasing the execution time of the application program, limiting the size of the loop body, and the loop body cannot map all the reconfigurable arrays at one time. Reduced execution time and increased scale

Inactive Publication Date: 2010-01-20
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In the process of realizing the present invention, the inventors found that the prior art has at least the following disadvantages: the scale of the loop body is limited, and when the scale of the loop body is larger than the physical scale of the reconfigurable array, the loop body cannot be mapped to the reconfigurable array at one time. Reconfigurable arrays cannot take advantage of the characteristics of reconfigurable arrays that are good at performing cyclic tasks, which increases the execution time of the entire application

Method used

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  • Method for dividing cycle task by means of software and hardware and device thereof
  • Method for dividing cycle task by means of software and hardware and device thereof
  • Method for dividing cycle task by means of software and hardware and device thereof

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Embodiment 1

[0088] The execution process of the division algorithm is described below with a specific embodiment, and the specific execution process is as follows:

[0089] Taking the scale of the reconfigurable array as 4×4 as an example, that is, it can support the mapping of a maximum of 16 nodes. Among them, G1 represents a reconfigurable array, and G2 represents a main processor.

[0090] see image 3 The original graph in is the data flow graph of the loop body to be divided, and there are 18 nodes in the graph.

[0091] Figure 8 For the flow chart of the method for dividing the software and hardware of the cyclic task provided by the embodiment of the present invention, see Figure 8 .

[0092] Step S1: First, all nodes are executed on G1 by default.

[0093] That is, G1=18, G2=0.

[0094] Step S2: Determine whether the number of nodes on G1 is greater than the maximum number of nodes that G1 can support, if the number of nodes on G1 is greater than the maximum number of nodes...

Embodiment 2

[0134] see Figure 9 , which is a schematic diagram of an apparatus for implementing software and hardware division of cyclic tasks provided by an embodiment of the present invention, Figure 10 It is a specific schematic diagram of a device for realizing software and hardware division of cyclic tasks provided by the embodiment of the present invention, which is used to perform software and hardware division of large-scale cyclic bodies, including:

[0135] The scheduling module 101 is configured to perform operator scheduling on nodes currently executing data streams of the reconfigurable array.

[0136] Among them, specifically include:

[0137] The first scheduling unit 101A is configured to perform first operator scheduling on nodes currently executing data flows;

[0138] The second scheduling unit 101B is configured to perform second operator scheduling on the node currently executing the data flow;

[0139] Correspondingly, the scheduling module specifically includes...

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Abstract

The invention discloses a method for dividing a cycle task by means of software and hardware and a device thereof, belonging to the field of an embedded system. When the number of nodes of data stream currently executed by a reconfigurable array is larger than the scale of the reconfigurable array, the method comprises the following steps: adjusting the nodes of the data stream currently executed by the reconfigurable array by means of arithmetic operators; according to the adjusting result of the arithmetic operators, obtaining the free degree of the input nodes; obtaining the output number of the input nodes; obtaining the input node with highest free degree and least output numbers according to the obtained free degree of the input nodes and the obtained output number of the input nodes; and dividing the obtained input nodes to a main processor. The method enlarges the scale of a cycle body which can be executed by a reconfigurable processor, plays the characteristic that the reconfigurable array is good at executing the cycle task, reduces the executing time of a whole application program, and meets the requirement in practical application.

Description

technical field [0001] The invention relates to the field of embedded systems, in particular to a method and device for realizing software and hardware division of cyclic tasks. Background technique [0002] With the increasing level of chip integration, a large number of functional modules can be integrated in one chip to form a system-on-chip. The integrated functional module often includes a processor module and a hardware acceleration module. How to make the processor and the hardware acceleration module work together is a problem that needs to be solved in the software-hardware co-design of the SoC. The software-hardware division is the basis of software-hardware co-design, and an application program is divided into processors and hardware acceleration modules to be executed separately. Wherein, the part executed by the processor is called the "software" part, and the part executed by the hardware acceleration module is called the "hardware" part. The quality of softw...

Claims

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Application Information

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IPC IPC(8): G06F9/50
Inventor 刘雷波王延升尹首一于苏东魏少军
Owner SHENZHEN PANGO MICROSYST CO LTD
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