Realizing method of configuration information for generating cycle task and device thereof

A task configuration and node technology, applied in the direction of multi-programming devices, resource allocation, etc., can solve the problem of increasing the time for reconfigurable arrays to transmit configuration information, the inability to realize computing functions quickly, and reducing the processing efficiency of reconfigurable arrays, etc. problem, achieve the effect of improving processing efficiency and reducing the time for transmitting configuration information

Inactive Publication Date: 2010-01-20
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] After the reconfigurable array executes the software and hardware division of the cyclic tasks, when the length of the critical path of the data flow graph currently executed by the reconfigurable array is greater than the number of rows of the reconfigurable array itself, the existing technology will divide the cyclic tasks into multiple batches. Mappin

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  • Realizing method of configuration information for generating cycle task and device thereof
  • Realizing method of configuration information for generating cycle task and device thereof
  • Realizing method of configuration information for generating cycle task and device thereof

Examples

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Embodiment 1

[0104] The present invention takes Figure 5 Take the data flow graph of , as an example, the input is: 4×4RCA; data flow graph G1, the number of nodes is 16 (16 Figure 8 For the flow chart of the method for implementing the method of generating cyclic task configuration information provided by the embodiment of the present invention, see Figure 8 ,Specific steps are as follows:

[0105] Step 101: Perform "as early as possible" operator scheduling on G1 to obtain the scheduled data flow graph.

[0106] Among them, the scheduled data flow diagram is as follows Figure 6 As shown in the figure on the left, according to the "as early as possible" operator scheduling and the scheduling relationship that the slave path must obey the critical path, assign nodes "2" and "11" to the first clock cycle; assign node "6" to the 2nd clock cycle; assign node "9" to the 3rd clock cycle; assign node "12" to the 4th clock cycle; assign node "14" to the 5th clock cycle; due to node "14" It ...

Embodiment 2

[0135] see Figure 9 , which is a schematic diagram of an apparatus for generating cyclic task configuration information provided by an embodiment of the present invention, Figure 10 A specific schematic diagram of an apparatus for generating configuration information for cyclic tasks provided by an embodiment of the present invention, including:

[0136] Scheduling module 201: used to perform operator scheduling on nodes currently executing data streams of the reconfigurable array.

[0137] Among them, the scheduling module specifically includes:

[0138] The first scheduling unit 201A is configured to perform first operator scheduling on nodes currently executing data flows;

[0139] The second scheduling unit 201B is configured to perform second operator scheduling on the node currently executing the data flow;

[0140] Correspondingly, when the obtaining module obtains the degree of freedom of each node, according to the clock cycle of the node in the second operator s...

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Abstract

The invention discloses a realizing method of configuration information for generating a cycle task and a device thereof, belonging to the field of an embedded system. When the scale of data stream is not larger than that of a reconfigurable array, the method comprises the following steps of: adjusting nodes of data stream currently executed by the reconfigurable array by means of arithmetic operators; according to the adjusting result of the arithmetic operators, obtaining the length of a key route, the free degree of the each node, and the clock period of the each node; according to the length of the key route and the columns of the reconfigurable array, setting up a matrix; when the data stream has unmapped nodes, according to the free degree of the unmapped nodes, the clock period of the unmapped nodes and a mapping rule, mapping the unmapped nodes into the matrix; and according to a mapping result, obtaining the configuration information of the cycle task on the reconfigurable array. The scheme only generates a set of configuration information of the reconfigurable array, reduces the time that transmits the configuration information to the reconfigurable array, and improves efficiency.

Description

technical field [0001] The invention relates to the field of embedded systems, in particular to a method and device for realizing generating cycle task configuration information. Background technique [0002] With the increasing level of chip integration, a large number of functional modules can be integrated in one chip to form a system-on-chip. The integrated functional module often includes a processor module and a hardware acceleration module. How to make the processor and the hardware acceleration module work together is a problem that needs to be solved in the software-hardware co-design of the SoC. [0003] Among them, the reconfigurable processor is composed of a main processor and a reconfigurable array. Such as figure 1 As shown, the division of software and hardware of the reconfigurable processor refers to dividing the application program into a software part executed on the main processor and a hardware part executed on the reconfigurable array. Typically, th...

Claims

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Application Information

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IPC IPC(8): G06F9/50
Inventor 刘雷波王延升尹首一于苏东魏少军
Owner SHENZHEN PANGO MICROSYST CO LTD
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