Dynamic reconfigurable processor

Abstract

The invention provides a dynamic reconfigurable processor, which comprises an input buffer, a first calculation routing unit, a reconfigurable array, a plurality of second calculation routing unit, a third calculation routing unit and an output buffer, wherein the input buffer is used for buffering external data, and outputting the data to the first calculation routing unit; the first calculation routing unit is used for receiving the data of the input buffer, computing the data, and outputting computation result data to a reconfigurable array; the reconfigurable array is used for computing the input data, and outputting computation result data to the third calculation routing unit, and comprises a plurality of reconfigurable units for completing computing operation of the input data; the second calculation routing units are used for completing connection of data between the reconfigurable units and computing the data; the third calculation routing unit is used for receiving output data of the reconfigurable array, and computing the data; and the output buffer is used for receiving result data output by the third calculation routing unit, and outputting the data to an external device.

Description

technical field [0001] The present application relates to the technical field of embedded systems, in particular to a dynamically reconfigurable processor. Background technique [0002] Dynamic reconfigurable processor is a new processor architecture, which has significant advantages over traditional single-core processors, dedicated chips, and field programmable logic arrays. It is a direction for the development of future circuit structures. [0003] First of all, a dynamically reconfigurable processor often contains multiple arithmetic logic units, and the number is huge, which is called a many-core array. The array is equipped with a highly flexible routing unit to realize the diverse interconnection between the arithmetic and logic units. Therefore, the many-core array connected by the routing unit can realize high-speed processing of data streams, and has a huge advantage in performance compared with traditional single-core and few-core processors. At the same time, ...

AI Technical Summary

Problems solved by technology

[0006] In the traditional dynamic reconfigurable processor, all operations on data are performed by reconfigurable units, but the delays of different reconfigurable unit calculation paths in reconfigurable arrays are inconsistent, and some of them are composed of AND, OR, and NOT. For simple combinational logic, shifting and other simple operations, the delay of the calculation path is very short and does not need to take up a beat. Therefore, performing these simple operations through reconfigurable units will cause waste of reconfigurable units and reduce the cost of reconfigurable units. The working efficiency of the array; secondly, for data processing operations such as matrix transposition and data splicing that consume a long number of beats, it needs to be mapped on the reconfigurable unit for operation. This operation takes up a large number of reconfigurable units, but for the array The usage efficiency is relatively low, which will also cause waste of reconfigurable units

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