Pulse coupling based silicon-nanowire complementary metal oxide semiconductors (CMOS) neuronal circuit

Abstract

The invention discloses a pulse coupling based silicon-nanowire CMOS (complementary metal oxide semiconductors ) neuronal circuit, which consists of a dendrite circuit, an integral summer and a pulse generating circuit, and the dendrite circuit, the integral summer and the pulse generating circuit are sequentially connected. The invention is characterized in that the outputs and inputs of the neuronal circuit are all pulse trains, and the components of the neuronal circuit are all silicon-nanowire CMOS transistors; the dendrite circuit is a CMOS circuit consisting of a set of parallelly-connected P-type nanowire MOS (metal oxide semiconductor ) transistors and an N-type nanowire MOS transistor which are connected in series by drain-terminal nodes, and the source terminals of the P-type nanowire MOS transistors input pulse voltage signals; the integral summer consists of a capacitor C sigma, and the capacitor is connected with the drain-terminal nodes of the P-type and N-type nanowire MOS transistors in the dendrite circuit and used for accumulating and weighting currents so as to form trigger voltage signals; and the pulse generating circuit is a feedback loop consisting of a plurality of even numbered serially-connected CMOS phase inverters and a dendrite CMOS circuit, and used for producing and outputting pulse trains, wherein the output frequency of the pulse trains is modulated by the input voltage pulse signals.

Description

technical field [0001] The invention relates to the technical field of nanometer neuron circuits, in particular to a silicon nanowire CMOS neuron circuit based on pulse coupling. Background technique [0002] Over the past 30 years, integrated circuit technology has developed following Moore's law, and traditional planar CMOS transistors have been scaled down from micrometers to nanometers. Currently, CPU chips based on 45nm gate-length planar CMOS transistors have been commercialized. However, scaling down of planar CMOS devices results in reduced switching performance and increased power density. Low cost, low power consumption, and high integration continue to drive the nanoscale process of CMOS devices. The development of nanometer CMOS transistors from planar structure to three-dimensional nanowire structure has become a trend. Fin-gate silicon nanowire transistors (FinFETs) based on SOI exhibit excellent gate control capability, which is close to the ideal switching ...

AI Technical Summary

Problems solved by technology

However, there are still many disadvantages when applying the PCNN network model to image segmentation, such as difficult to determine network coefficients, complex pulse threshold processing, and undetermined number of iterations, etc., especially the pulse threshold in the model is according to the exponential law Attenuation, although this change law is in line with the nonlinear characteristics of the human eye's response to brightness intensity, when computer processing, time needs to be divided into discrete time periods, and the division of time periods not only directly affects the processing speed and segmentation effect

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