25 results about "3d memory" patented technology

A 3D memory device includes a memory stack having alternating stacked conductive layers and stacked dielectric layers, a semiconductor layer, and a channel structure extending vertically through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel. A first doping concentration of a portion of the semiconductor channel in the first portion of the channel structure is greater than a second doping concentration of a portion of the semiconductor channel in the second portion of the channel structure.

Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. A disclosed 3D memory device can comprise an alternating conductive / dielectric stack on a substrate, a plurality of channel structures in the alternating conductive / dielectric stack, and a plurality of gate line slit (GLS) structures in the alternating conductive / dielectric stack. Each GLS structure can include a plurality of first type GLS portions penetrating the alternating conductive / dielectric stack, and a plurality of second type GLS portions in an upper portion of the alternating conductive / dielectric stack.

A three-dimensional (3D) memory structure is described. The 3D memory structure includes a first memory die having first multilayer contact pads including a first outer pad composed of a first conductive material. The 3D memory structure also includes a base logic die including second multilayer contact pads having a second outer pad composed of the first conductive material. The 3D memory structure further includes hybrid bonding links coupled between the second outer pad of the second multilayer contact pads of the base logic die and the first outer pad of the first multilayer contact pads of the first memory die. The hybrid bonding links are composed of the first conductive material.

A three-dimensional (3D) memory device and a fabricating method thereof are disclosed. The 3D memory device can comprise an array of memory cells. Each memory cell can comprise a capacitor and a vertical transistor. The vertical transistor can comprise a semiconductor body extending in a vertical direction and in contact with the capacitor, and a three-sided gate structure surrounding the semiconductor body from three lateral directions. The 3D memory device can further comprise a memory controller configured to control the array of memory cells.

Various three-dimensional memory cell structures, array architectures, and fabrication processes are disclosed. In an example process, first and second sacrificial layers having different etch selectivities are alternately deposited to form a multilayer stack, and vertical openings are etched through the stack. Portions of the first sacrificial layers are selectively removed through the openings to form lateral recesses. Semiconductor material is deposited to fill the lateral recesses and the vertical openings and is anisotropically etched to re-form the vertical openings while retaining semiconductor material in the recesses as channel regions. The re-formed openings are filled with conductor material to form vertical bit lines coupled to the channel regions. The first sacrificial layers are removed, and the resulting spaces are filled to form a source line layer, and the second sacrificial layers are removed to form spaces in which gate dielectric and gate conductor materials are formed adjacent to the channel regions.

Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device includes a first semiconductor structure. The first semiconductor structure includes an array of first type through stack structures in a first region of a memory stack, an array of second type through stack structures in a second region of the memory stack, a semiconductor layer including a first portion on the array of first type through stack structures and a second portion on the array of second type through stack structures, multiple vias each penetrating the semiconductor layer and in contact with a corresponding one of the first type through stack structures or the array of second type through stack structures, and a slit structure separating the array of first type through stack structures from the array of second type through stack structures, and separating the first portion of the semiconductor layer from the second portion of the semiconductor layer.

A three-dimensional (3D) memory structure is described. The 3D memory structure includes a first memory die having first multilayer contact pads including a first outer pad composed of a first conductive material. The 3D memory structure also includes a base logic die including second multilayer contact pads having a second outer pad composed of the first conductive material. The 3D memory structure further includes hybrid bonding links coupled between the second outer pad of the second multilayer contact pads of the base logic die and the first outer pad of the first multilayer contact pads of the first memory die. The hybrid bonding links are composed of the first conductive material.

The present disclosure provides a configuration method, a reading method and a 3D memory. The configuration method comprises writing data in a plurality of selected memory cells corresponding to a selected word line, measuring threshold voltages of the selected memory cells to obtain a relationship table, and writing the relationship table into a configuration block. The reading method comprises obtaining a data reading request to determine a memory block where data to be read is located, reading a selected word line thereof to obtain a number of memory cells corresponding to the selected word line and having threshold voltages less than a first predetermined voltage, searching the relationship table in the configuration block to obtain a turn-on voltage corresponding thereto, applying the turn-on voltage on a non-reading word line, and applying a reading voltage on a reading word line to obtain the data to be read. The 3D memory using the configuration method and the reading method can dynamically reduce the turn-on voltage of the memory cells to reduce read disturbance caused by the read operation.

Methods and devices for a lateral three-dimensional memory device, are described herein. One method includes forming a thin film transistor including a first thermal process having a first range of temperatures, forming a capacitor bottom electrode of a capacitor structure including a second thermal process having a second range of temperature, wherein a maximum temperature in the second range of temperatures is less than a maximum temperature in the first range of temperatures, forming a CMOS structure including a third thermal process having a third range of temperatures, wherein a maximum temperature in the third range of temperatures is less than a maximum temperature in the second range of temperatures, and forming at least one other part of the capacitor structure.

A method for manufacturing a memory device is provided. The method comprises forming a first epitaxial layer on a substrate and forming a memory array on the first epitaxial layer, the memory array comprising a memory stack of alternating layers of oxide material and metal material on the first epitaxial layer, at least one memory cell extending from the first epitaxial layer through the memory stack, and a slit filled with a filler material adjacent to the at least one memory cell.

Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device includes a first semiconductor structure. The first semiconductor structure includes an array of first-type through stack structures in a first region and an array of second-type through stack structures in a second region, and a slit structure separating the array of first-type through stack structures from the array of second-type through stack structures. The 3D memory device further includes a second semiconductor structure. The second semiconductor structure includes a first periphery circuit and a second periphery circuit at different levels. The second semiconductor structure and the first semiconductor structure are bonded together, such that the first periphery circuit is located between the second periphery circuit and the first semiconductor structure.

This application relates to the field of semiconductor memory device technology, and discloses a 3D memory device and its fabrication process. The 3D memory device includes a substrate, a multilayer stacked structure, a contact lead-out structure, a via, a resistive switching functional layer, and a top electrode. The multilayer stacked structure includes multiple alternating layers of two-dimensional conductive material and multiple layers of insulating dielectric material arranged in a vertical direction. The two-dimensional conductive material layers serve as interlayer contact electrodes or memory cell electrodes. The via penetrates at least a portion of the multilayer stacked structure and exposes the edge regions of the two-dimensional conductive material layers. The resistive switching functional layer is disposed on the inner wall and / or inside the via and contacts the edge regions of the two-dimensional conductive material layers. The top electrode is electrically connected to the resistive switching functional layer. This structure utilizes the two-dimensional conductive material layers to reduce the vertical thickness of the interlayer electrodes and forms multiple resistive switching memory cells on the sidewalls of the vias, thereby increasing the storage density of the 3D memory device.

The present disclosure relates to a method for manufacturing a 3D memory device, and particularly, to a method for manufacturing high capacity and high performance 3D NAND flash memory device. The method includes: alternately stacking sacrificial layers and insulating layers; forming a channel through hole through the sacrificial layers and the insulating layers; lining the channel through hole with an initial blocking layer; and performing an oxidation treatment, for turning the initial blocking layer to a blocking oxide layer. A gas source for the oxidation treatment includes a reaction gas having hydrogen and oxygen, and includes an ionization enhancement gas formed by a first type ionization enhancement gas, a second type ionization enhancement gas or a combination thereof. The first type ionization enhancement gas includes at least one in a group consist of tritium, ozone and H2O. The second type ionization enhancement gas includes at least one inert gas.

A 3D memory and its fabrication method are disclosed. The fabrication method of the 3D memory includes: forming a stacked structure comprising alternating sacrificial layers and conductive layers; forming vias penetrating the stacked structure, the vias including a plurality of first sub-vias located in the sacrificial layers and a plurality of second sub-vias located in the conductive layers, wherein the orthographic projection of the first sub-vias falls within the orthographic projection of the second sub-vias on a plane parallel to the substrate; forming a semiconductor layer, a gate insulating layer, and a gate electrode within the vias, wherein the gate electrode of the transistors in different layers is part of the word line; etching away the sacrificial layers to expose the semiconductor layers located within the first sub-vias; and etching away the semiconductor layers located within the first sub-vias. The solution provided in this embodiment, by setting sacrificial layers between layers, achieves etching of the semiconductor layers between layers, reducing parasitic capacitance and improving device performance.

A method for fabricating a semiconductor device comprising: forming a first level; disposing a second level on top of the first level; disposing a third level on top of the second level; forming a via connection through the second level and the third level, where the first level comprises first transistors, at least four independently controlled first memory arrays, and first filled holes therein, where the second level comprises second memory arrays and second filled holes therein, where disposing the third level comprises third transistors, a plurality of third memory arrays, and at least one metal layer therein; disposing a fourth level on top of the third level, where the fourth level comprises fourth transistors and at least one SRAM memory array therein; and bonding the fourth level to the third level via metal-to-metal bonding regions.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In one example, a 3D memory device includes a multi-layer stacked structure, where the multi-layer stacked structure includes a plurality of alternately stacked conductive layers and dielectric layers. The 3D memory device further includes a semiconductor layer over the multi-layer stacked structure, and a plurality of channel structures penetrating into the multi-layer stacked structure and the semiconductor layer. A first end of each channel structure is located within the semiconductor layer, and the first ends of the channel structures are aligned with one another.

Embodiments of a three-dimensional (3D) memory device and a method for forming the same are disclosed. In one example, a 3D memory device includes: a substrate; a memory stack layer located on the substrate; a plurality of channel structures, each extending perpendicularly through the memory stack layer; an isolation structure; and alignment marks. The memory stack layer includes a plurality of interleaved conductor layers and dielectric layers. The outermost conductor layer among the conductor layers facing the substrate is a source select gate line (SSG). The isolation structure extends perpendicularly into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG from the at least one channel structure. The alignment marks extend perpendicularly into the substrate and are coplanar with the isolation structure.

In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region and word line pick-up structures in a first portion of a second region. The first region and the second region are arranged in a first direction. The 3D memory device also includes word lines each extending in the first region and a second portion of the second region. The first portion and the second portion of the second region are arranged in a second direction perpendicular to the first direction. The 3D memory device also includes dummy channel structures in the second portion of the second region. Adjacent channel structures are spaced apart from each other by a first distance. Adjacent dummy channel structures are spaced apart from each other by a second distance that is smaller than the first distance.

Provided is a sidewall doping method for a 3D (three dimensional) memory device, which belongs to the technical field of memory device manufacturing. The sidewall doping method for the 3D memory device mainly includes: conducting deposition treatment on a sidewall of the 3D memory device; conducting annealing treatment by either a long-wavelength radiation annealing process or a rapid thermal annealing process; and removing a capping layer portion by using an anisotropic SiO2 selective and specific vertical etching process; where the above deposition, annealing and etching steps are repeated for a predetermined number of cycles to complete sidewall doping.

The present disclosure relates to a layered CiM architecture system, a scheduling method, an apparatus, a device and a storage medium. The method comprises: a control layer and a 3D memory-in-compute array connected vertically, the 3D memory-in-compute array is integrated with a plurality of memory-compute layers for different modalities; the control layer is used for modal perception on acquired modal data, and the modal data is scheduled to a memory-compute layer in the 3D memory-in-compute array according to the result of the modal perception; the 3D memory-in-compute array is used for selecting a memory-compute layer corresponding to the modal data to infer the modal data according to the processing requirement of the modal data after receiving the modal data. The unreasonable bottleneck of bandwidth allocation of data loading is broken, the efficiency, energy efficiency and long-time running stability of edge multi-modal inference are significantly improved, and the resource constraints of edge scenarios are fully adapted.

A method for fabricating a 3D memory device includes forming a sacrificial layer over a substrate, forming a first dielectric stack over the sacrificial layer, forming a channel hole structure, forming an opening that exposes the sacrificial layer, removing the sacrificial layer to create a cavity and expose a part of the channel hole structure, forming a semiconductor layer to fill the cavity, filling the opening with a filling structure, and forming a second dielectric stack over the filling structure. The opening is made for a gate line slit (GLS) structure.

The present disclosure relates to a three-dimensional memory device having parallel trench capacitors. A 3D memory device is provided. The 3D memory device can include a logic device layer on a substrate and a memory device layer stacked on the logic device layer. The logic device layer can include logic devices disposed on the substrate. The memory device layer can include a word line stack disposed in an extended region, a staircase pattern disposed in the word line stack, a dielectric layer stack in a peripheral region, and a capacitor embedded in the dielectric layer stack.

Embodiments of 3D memory devices and methods of forming and operating the same are disclosed. In an example, a 3D memory device includes a memory stack, a plurality of memory strings, a plurality of bit line contacts each in contact with a respective one of the plurality of memory strings. The memory stack includes interleaved conductive layers and dielectric layers. Each of the memory strings extends vertically through the memory stack. The conductive layers include a plurality of drain select gate (DSG) lines configured to control drains of the plurality of memory strings. The plurality of memory strings is divided into a plurality of regions that are the smallest repeating units of the memory stack in a plan view. Each of the plurality of memory strings is adjoined to at least one of the DSG lines.