87 results about "3d memory" patented technology

Described are memory devices having an array region and an extension region adjacent the array region. The array region includes at least two unit cells stacked vertically. The extension region includes a memory stack and a plurality of word line contacts. The memory stack comprises alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. The plurality of word line contacts extend through the memory stack to the at least one conductive layer. Each of the plurality of word line contacts have a height that is different than the height of an adjacent word line contact. Each of the plurality of word line contacts has a metallization layer on the top surface. Methods of forming a memory device are described.

A 3D memory device includes a memory stack having alternating stacked conductive layers and stacked dielectric layers, a semiconductor layer, and a channel structure extending vertically through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel. A first doping concentration of a portion of the semiconductor channel in the first portion of the channel structure is greater than a second doping concentration of a portion of the semiconductor channel in the second portion of the channel structure.

This invention provides a wafer matching method and apparatus, a fabrication method, an electronic device, and a storage medium. The wafer matching method includes: obtaining a set of influence factors for multiple first wafers and multiple second wafers; obtaining a set of principal component factors by dimensionality reduction based on the set of influence factors; determining the degree of matching between each first wafer and each second wafer based on the set of principal component factors; and selecting a second wafer that matches the first wafer from the multiple second wafers based on the degree of matching. This invention not only reduces the workload in determining the degree of matching between wafers by using the set of principal component factors to represent all influence factors, thus improving the production efficiency of 3D memory, but also ensures optimal and stable matching between the first and second wafers by matching the degree of matching, thereby improving the reliability of 3D memory devices fabricated by bonding processes.

Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. A disclosed 3D memory device can comprise an alternating conductive / dielectric stack on a substrate, a plurality of channel structures in the alternating conductive / dielectric stack, and a plurality of gate line slit (GLS) structures in the alternating conductive / dielectric stack. Each GLS structure can include a plurality of first type GLS portions penetrating the alternating conductive / dielectric stack, and a plurality of second type GLS portions in an upper portion of the alternating conductive / dielectric stack.

A 3D memory device including a stacked structure, a first group of channel structures and a second group of channel structures, a partition structure and at least one support structure is provided. The stacked structure includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A top surface of the stacked structure is parallel to a plane defined by a first direction and a second direction. The first group of channel structures and the second group of channel structures penetrate the stacked structure and are arranged along a first direction. The partition structure includes a plurality of discrete partition structures and is disposed between the first group of channel structures and the second group of channel structures. The plurality of discrete partition structures are arranged along the second direction and penetrate the stacked structure. At least one support structure is disposed between the adjacent discrete partition structures. The 3D memory device is a 3D NAND flash memory device with high capacity and performance.

A three-dimensional (3D) memory device includes a stacked structure having interleaved conductive and dielectric layers, and a channel structure extending through the stacked structure in a first direction. The channel structure contacts the source electrode of the 3D memory device at its bottom. The channel structure includes a semiconductor channel and a memory film over the semiconductor channel. The memory film includes a first angular structure, and a first diameter of the memory film at its bottom below the first angular structure is smaller than a second diameter of the memory film at its upper portion above the first angular structure.

A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. At least one DRAM cell unit includes a transistor and a capacitor. The capacitor includes a first metal layer, a capacitor dielectric layer positioned on the first metal layer, and a second metal layer positioned on the capacitor dielectric layer. The capacitor is elongated in a horizontal direction parallel to the working surface of the substrate. The second metal layer has a first end and a second end in the horizontal direction. The transistor includes a channel structure, and a gate structure disposed all around the channel structure. The first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor.

The application discloses a 3D memory device and a manufacturing method thereof. The 3D memory device comprises a chip storage area, the chip storage area comprises: a stack structure on a semiconductor substrate; a plurality of gate line gaps penetrating through the stack structure, part of the gate line gaps divide the chip storage area into a plurality of block storage areas, the plurality of gate line gaps are arranged along a first direction, and a plurality of channel columns penetrating through the stack structure are arranged between adjacent gate line gaps, the chip storage area comprises a central area and at least one edge area arranged along the first direction, and the minimum distance between at least one gate line gap and its adjacent channel column in the at least one edge area is greater than the minimum distance between at least one gate line gap and its adjacent channel column in the central area. By increasing the minimum distance between the gate line gap and its adjacent channel column in the edge area, the influence of stress and load effect on the 3D NAND device is avoided, and the low reliability and low yield of the 3D NAND device are avoided.

The present invention relates to the technical field of memory fabrication, and provides a method for doping a side wall of a 3D memory device. The main steps thereof comprise: performing a deposition treatment on the side wall of a 3D memory device; performing an annealing treatment by means of a longwave-light annealing process or a rapid thermal annealing process; and etching away a capping layer portion by means of a longitudinal etching process for the anisotropic selective specific etching of SiO2, and cyclically repeating the above steps of deposition, annealing and etching a predetermined number of times to finish the doping of the side wall. The present invention can complete the doping of the side wall of a deep trench of a 3D memory device at a deep-submicron-scale or nanometer-scale depth, and can form a buffer layer with an accurately controllable depth or concentration.

This invention provides a step structure within a three-dimensional memory device and a method for forming it. [Solution] An embodiment of a 3D memory device having a staircase structure and a method for forming the same are disclosed. In the example, the 3D memory device comprises a memory array structure and a staircase structure located in the middle of the memory array structure, which laterally divides the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone includes a first pair of stairs facing each other in the first lateral direction and at different depths. Each staircase comprises a plurality of steps. At least one step in the first pair of stairs is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

An AI inference platform comprises a logic die including an array of AI processing elements. Each AI processing element including an activation memory storing activation data for use in neural network computations. The platform includes a memory die that includes an array of 3D memory cells and a page buffer that facilitates storage and retrieval of neural network weights for use in neural network computations. A plurality of vertical connections can directly connect AI processing elements in the logic die and page buffers of corresponding ones of the memory cells in the memory die, enabling storage or retrieval of a neural network weight to and from a particular page buffer of a corresponding 3D memory cell for use in neural network computations conducted by a corresponding AI processing element in the logic die.

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a first angled structure, and a first diameter of the memory film at the bottom portion below the first angled structure is smaller than a second diameter of the memory film at an upper portion above the first angled structure.

An apparatus includes a memory controller configured to receive, from a three-dimensional (3D) memory device, first temperature information associated with a first bank of the 3D memory device and to receive, from the 3D memory device, second temperature information associated with a second bank of the 3D memory device. The first bank and the second bank are associated with a common rank of the 3D memory device. The memory controller is further configured to provide, to the 3D memory device, a first refresh command associated with the first bank and to provide, to the 3D memory device, a second refresh command associated with the second bank. The first refresh command is associated with a first refresh interval that is different than a second refresh interval associated with the second refresh command.

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes, in each of the plurality of petals, a semiconductor channel and a channel plug above and in contact with the semiconductor channel.

A three-dimensional (3D) memory structure is described. The 3D memory structure includes a first memory die having first multilayer contact pads including a first outer pad composed of a first conductive material. The 3D memory structure also includes a base logic die including second multilayer contact pads having a second outer pad composed of the first conductive material. The 3D memory structure further includes hybrid bonding links coupled between the second outer pad of the second multilayer contact pads of the base logic die and the first outer pad of the first multilayer contact pads of the first memory die. The hybrid bonding links are composed of the first conductive material.

A three-dimensional (3D) memory device and a fabricating method thereof are disclosed. The 3D memory device can comprise an array of memory cells. Each memory cell can comprise a capacitor and a vertical transistor. The vertical transistor can comprise a semiconductor body extending in a vertical direction and in contact with the capacitor, and a three-sided gate structure surrounding the semiconductor body from three lateral directions. The 3D memory device can further comprise a memory controller configured to control the array of memory cells.

Provided is a three-dimensional (3D) memory device including: a substrate, a stack structure, and a vertical channel pillar. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately. The vertical channel pillar penetrates through the stack structure. The vertical channel pillar includes a first source / drain pillar and a channel layer laterally surrounding the first source / drain pillar. The first source / drain pillar includes a first buffer pillar and a first semiconductor layer having a first conductivity type wrapping the first buffer pillar. The channel layer includes a polysilicon layer having a second conductivity type different from the first conductivity type. In some embodiments, the 3D memory device may be, but is not limited to, a AND flash memory.

A three-dimensional (3D) memory device is disclosed. The 3D memory device includes a memory stack, a semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack, and a source contact above the memory stack and in contact with the semiconductor layer. A semiconductor plug, in contact with the semiconductor layer, surrounds an end of one of the channel structures. The source contact is electrically connected with the one of the channel structures. At least a portion of the source contact is buried within the semiconductor layer.

Methods for input / output voltage training of a three-dimensional (3D) memory device can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.

A method for neural network processing, the method may include applying, by a neural network processor, a group of neural network kernels of respective layers of a neural network to provide neural network output results. The applying may include applying a (2D) kernel of the group of kernels on 2D layer input values of a first layer of the neural network to provide first layer output values. The applying may include scanning the 2D layer input values with the 2D kernel. The scanning may include flattening the 2D kernel, flattening the 2D layer input values, and storing first layer output values in a 3D memory unit. The applying may also include applying a 3D kernel of the group of kernels, on 3D layer input values of a second layer of the neural network to provide second layer output values, wherein the applying comprises scanning at least one feature vector of the 3D layer input values with at least one vector of the 3D kernel.

Various three-dimensional memory cell structures, array architectures, and fabrication processes are disclosed. In an example process, first and second sacrificial layers having different etch selectivities are alternately deposited to form a multilayer stack, and vertical openings are etched through the stack. Portions of the first sacrificial layers are selectively removed through the openings to form lateral recesses. Semiconductor material is deposited to fill the lateral recesses and the vertical openings and is anisotropically etched to re-form the vertical openings while retaining semiconductor material in the recesses as channel regions. The re-formed openings are filled with conductor material to form vertical bit lines coupled to the channel regions. The first sacrificial layers are removed, and the resulting spaces are filled to form a source line layer, and the second sacrificial layers are removed to form spaces in which gate dielectric and gate conductor materials are formed adjacent to the channel regions.

3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.

3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.

Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device includes a first semiconductor structure. The first semiconductor structure includes an array of first type through stack structures in a first region of a memory stack, an array of second type through stack structures in a second region of the memory stack, a semiconductor layer including a first portion on the array of first type through stack structures and a second portion on the array of second type through stack structures, multiple vias each penetrating the semiconductor layer and in contact with a corresponding one of the first type through stack structures or the array of second type through stack structures, and a slit structure separating the array of first type through stack structures from the array of second type through stack structures, and separating the first portion of the semiconductor layer from the second portion of the semiconductor layer.

A variety of applications can include an apparatus having a three-dimensional (3D) memory device with sub-access line drivers to access lines embedded in a memory array of the 3D memory device. A sub-access line driver to an access line to a tier of memory cells of the memory array can include two transistors coupled to each other and the access line. A first transistor of the two transistors can be coupled at one end of the access line and the second transistor of the two transistors can be coupled at the other end of the access.

A three-dimensional (3D) memory structure is described. The 3D memory structure includes a first memory die having first multilayer contact pads including a first outer pad composed of a first conductive material. The 3D memory structure also includes a base logic die including second multilayer contact pads having a second outer pad composed of the first conductive material. The 3D memory structure further includes hybrid bonding links coupled between the second outer pad of the second multilayer contact pads of the base logic die and the first outer pad of the first multilayer contact pads of the first memory die. The hybrid bonding links are composed of the first conductive material.

Described are memory devices having an array region and an extension region adjacent the array region. The array region includes at least two unit cells stacked vertically. The extension region includes a memory stack and a plurality of word line contacts. The memory stack comprises alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. The plurality of word line contacts extend through the memory stack to the at least one conductive layer. Each of the plurality of word line contacts have a height that is different than the height of an adjacent word line contact. Each of the plurality of word line contacts has a metallization layer on the top surface. Methods of forming a memory device are described.

The present disclosure relates to memory array test structures and methods of forming the same. Disclosed are test structures for 3D memory arrays and methods of forming the same. In one embodiment, a memory array includes a first word line located over a semiconductor substrate and extending in a first direction, a second word line located over the first word line and extending in the first direction, a memory film contacting the first word line and the second word line, an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being located between the OS layer and each of the first word line and the second word line, and a test structure located over the first word line and the second word line, the test structure including a first conductor electrically coupling the first word line to the second word line, the first conductor extending in the first direction.

A three-dimensional (3D) memory structure is described. The 3D memory structure includes a first memon die having a memory cell array coupled to a wordline-bitline fanout structure. Additionally, the 3D memory structure includes a second memory die having peripheral logic formed from a second semiconductor substrate. A backside of the second memory' die is hybrid bonded with a backside of the first memory die.

A three-dimensional (3D) memory device includes a memory array device, a peripheral device, an etch stop layer, and a backside gate line slit. The memory array device includes a frontside and a backside, a plurality of memory strings, and a plurality of word lines in a staircase structure coupled to the plurality of memory strings. The peripheral device is above the frontside of the memory array device. The etch stop layer is between the memory array device and the peripheral device. The backside gate line slit extends through the backside of the memory array device to the etch stop layer. The backside gate line slit includes a conductive gate line layer and an insulating gate line layer. The 3D memory device can increase manufacturing efficiency, increase yield, reduce thermal stress, reduce fluorine contamination, increase an overlay window, and decrease overlay errors.