163 results about "3d memory" patented technology

Described are memory devices having an array region and an extension region adjacent the array region. The array region includes at least two unit cells stacked vertically. The extension region includes a memory stack and a plurality of word line contacts. The memory stack comprises alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. The plurality of word line contacts extend through the memory stack to the at least one conductive layer. Each of the plurality of word line contacts have a height that is different than the height of an adjacent word line contact. Each of the plurality of word line contacts has a metallization layer on the top surface. Methods of forming a memory device are described.

Provided are a three-dimensional (3D) memory device using a self-selecting memory and / or an operation method of the 3D memory device. The 3D memory device may include a plurality of memory cells arranged in three dimensions on a substrate. Each of the plurality of memory cells may include a transistor and a self-selecting memory layer connected in series. The transistor may include a channel layer and the channel layer may be parallel to a surface of the substrate. The self-selecting memory layer may include a chalcogenide-based material having Ovonic threshold switching characteristics. The self-selecting memory layer may be configured to have a threshold voltage change according to a polarity and an intensity of an applied voltage.

A 3D memory device includes a memory stack having alternating stacked conductive layers and stacked dielectric layers, a semiconductor layer, and a channel structure extending vertically through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel. A first doping concentration of a portion of the semiconductor channel in the first portion of the channel structure is greater than a second doping concentration of a portion of the semiconductor channel in the second portion of the channel structure.

This invention provides a wafer matching method and apparatus, a fabrication method, an electronic device, and a storage medium. The wafer matching method includes: obtaining a set of influence factors for multiple first wafers and multiple second wafers; obtaining a set of principal component factors by dimensionality reduction based on the set of influence factors; determining the degree of matching between each first wafer and each second wafer based on the set of principal component factors; and selecting a second wafer that matches the first wafer from the multiple second wafers based on the degree of matching. This invention not only reduces the workload in determining the degree of matching between wafers by using the set of principal component factors to represent all influence factors, thus improving the production efficiency of 3D memory, but also ensures optimal and stable matching between the first and second wafers by matching the degree of matching, thereby improving the reliability of 3D memory devices fabricated by bonding processes.

Provided are a semiconductor structure which may be used in a 3D AND flash memory and a manufacturing method thereof. The semiconductor structure includes a substrate having a memory device region including memory array and staircase regions and a peripheral region, a circuit structure layer and a first conductive layer sequentially on the circuit structure layer, a stacked structure including second conductive layers and insulating layers and having a staircase profile on the first conductive layer in the memory device region, an oxide layer on the first conductive layer, an insulating wall in the oxide layer, and dummy pillars in the peripheral and staircase regions. The insulating wall penetrates the first conductive layer and surrounds the stacked structure. Each dummy pillar in the peripheral region penetrates the oxide layer and the first conductive layer. Each dummy pillar in the staircase region penetrates the stacked structure and the first conductive layer.

A 3D memory device includes a plurality of mats that each include a memory array stacked over logic circuitry supporting operations of the memory array. The logic circuitry include a local column decoder under the memory array for selecting one or more local column select lines associated with a memory operation. The logic circuitry furthermore includes one or more selectable global array data bus redrivers for receiving global data signals from a set of global data signal buses, selecting one of the global data signal buses, and amplifying signals between the selected global data signal bus and a local data signal bus that communicates the data signals to and from the memory array. The 3D memory device supports concurrent sub-page accesses which may be interleaved for efficient memory operations.

Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. A disclosed 3D memory device can comprise an alternating conductive / dielectric stack on a substrate, a plurality of channel structures in the alternating conductive / dielectric stack, and a plurality of gate line slit (GLS) structures in the alternating conductive / dielectric stack. Each GLS structure can include a plurality of first type GLS portions penetrating the alternating conductive / dielectric stack, and a plurality of second type GLS portions in an upper portion of the alternating conductive / dielectric stack.

A three-dimensional 3D memory device includes a substrate, a peripheral device disposed on the substrate, a memory stack disposed above the peripheral device and including a plurality of conductor / dielectric layer pairs, and a plurality of memory strings, each of the memory strings extending through the memory stack. The peripheral device includes at least a transistor disposed on the substrate. The transistor includes a gate stack. The gate stack of the transistor includes a staircase structure, and an operational voltage of the transistor is above 5 volts.

Methods for input / output voltage training of a three-dimensional (3D) memory device is disclosed. The method can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.

A 3D memory device including a stacked structure, a first group of channel structures and a second group of channel structures, a partition structure and at least one support structure is provided. The stacked structure includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A top surface of the stacked structure is parallel to a plane defined by a first direction and a second direction. The first group of channel structures and the second group of channel structures penetrate the stacked structure and are arranged along a first direction. The partition structure includes a plurality of discrete partition structures and is disposed between the first group of channel structures and the second group of channel structures. The plurality of discrete partition structures are arranged along the second direction and penetrate the stacked structure. At least one support structure is disposed between the adjacent discrete partition structures. The 3D memory device is a 3D NAND flash memory device with high capacity and performance.

A three-dimensional (3D) memory device includes a stacked structure having interleaved conductive and dielectric layers, and a channel structure extending through the stacked structure in a first direction. The channel structure contacts the source electrode of the 3D memory device at its bottom. The channel structure includes a semiconductor channel and a memory film over the semiconductor channel. The memory film includes a first angular structure, and a first diameter of the memory film at its bottom below the first angular structure is smaller than a second diameter of the memory film at its upper portion above the first angular structure.

A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. At least one DRAM cell unit includes a transistor and a capacitor. The capacitor includes a first metal layer, a capacitor dielectric layer positioned on the first metal layer, and a second metal layer positioned on the capacitor dielectric layer. The capacitor is elongated in a horizontal direction parallel to the working surface of the substrate. The second metal layer has a first end and a second end in the horizontal direction. The transistor includes a channel structure, and a gate structure disposed all around the channel structure. The first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor.

The application discloses a 3D memory device and a manufacturing method thereof. The 3D memory device comprises a chip storage area, the chip storage area comprises: a stack structure on a semiconductor substrate; a plurality of gate line gaps penetrating through the stack structure, part of the gate line gaps divide the chip storage area into a plurality of block storage areas, the plurality of gate line gaps are arranged along a first direction, and a plurality of channel columns penetrating through the stack structure are arranged between adjacent gate line gaps, the chip storage area comprises a central area and at least one edge area arranged along the first direction, and the minimum distance between at least one gate line gap and its adjacent channel column in the at least one edge area is greater than the minimum distance between at least one gate line gap and its adjacent channel column in the central area. By increasing the minimum distance between the gate line gap and its adjacent channel column in the edge area, the influence of stress and load effect on the 3D NAND device is avoided, and the low reliability and low yield of the 3D NAND device are avoided.

The present invention relates to the technical field of memory fabrication, and provides a method for doping a side wall of a 3D memory device. The main steps thereof comprise: performing a deposition treatment on the side wall of a 3D memory device; performing an annealing treatment by means of a longwave-light annealing process or a rapid thermal annealing process; and etching away a capping layer portion by means of a longitudinal etching process for the anisotropic selective specific etching of SiO2, and cyclically repeating the above steps of deposition, annealing and etching a predetermined number of times to finish the doping of the side wall. The present invention can complete the doping of the side wall of a deep trench of a 3D memory device at a deep-submicron-scale or nanometer-scale depth, and can form a buffer layer with an accurately controllable depth or concentration.

Three-dimensional (3D) memory devices and methods of forming the same are disclosed. In a particular aspect, a 3D memory device includes a first semiconductor assembly, a second semiconductor assembly, and an inter-assembly bonding layer between the first semiconductor assembly and the second semiconductor assembly. The first semiconductor assembly includes a first array structure and a first peripheral structure. The first array structure includes a first memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The first peripheral structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor assembly includes a second array structure and a second peripheral structure. The second array structure includes a second memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The second peripheral structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.

One aspect of this description relates to a semiconductor device. In some embodiments, the semiconductor device includes a first drain / source structure extending in a first direction, a second drain / source structure extending the first direction and spaced from the first drain / source structure in a second direction perpendicular to the first direction, a third drain / source structure extending in the first direction and spaced from the second drain / source structure in the second direction, a first bit line disposed over the first drain / source structure in the first direction, a common select line that includes a portion disposed over the second drain / source structure in the first direction, a second bit line disposed over the third drain / source structure in the first direction, and a charge storage layer coupled to at least a first sidewall of each of the first drain / source structure, the second drain / source structure, and the third drain / source structure.

This invention provides a step structure within a three-dimensional memory device and a method for forming it. [Solution] An embodiment of a 3D memory device having a staircase structure and a method for forming the same are disclosed. In the example, the 3D memory device comprises a memory array structure and a staircase structure located in the middle of the memory array structure, which laterally divides the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone includes a first pair of stairs facing each other in the first lateral direction and at different depths. Each staircase comprises a plurality of steps. At least one step in the first pair of stairs is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

An AI inference platform comprises a logic die including an array of AI processing elements. Each AI processing element including an activation memory storing activation data for use in neural network computations. The platform includes a memory die that includes an array of 3D memory cells and a page buffer that facilitates storage and retrieval of neural network weights for use in neural network computations. A plurality of vertical connections can directly connect AI processing elements in the logic die and page buffers of corresponding ones of the memory cells in the memory die, enabling storage or retrieval of a neural network weight to and from a particular page buffer of a corresponding 3D memory cell for use in neural network computations conducted by a corresponding AI processing element in the logic die.

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a first angled structure, and a first diameter of the memory film at the bottom portion below the first angled structure is smaller than a second diameter of the memory film at an upper portion above the first angled structure.

An apparatus includes a memory controller configured to receive, from a three-dimensional (3D) memory device, first temperature information associated with a first bank of the 3D memory device and to receive, from the 3D memory device, second temperature information associated with a second bank of the 3D memory device. The first bank and the second bank are associated with a common rank of the 3D memory device. The memory controller is further configured to provide, to the 3D memory device, a first refresh command associated with the first bank and to provide, to the 3D memory device, a second refresh command associated with the second bank. The first refresh command is associated with a first refresh interval that is different than a second refresh interval associated with the second refresh command.

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes, in each of the plurality of petals, a semiconductor channel and a channel plug above and in contact with the semiconductor channel.

A three-dimensional (3D) memory structure is described. The 3D memory structure includes a first memory die having first multilayer contact pads including a first outer pad composed of a first conductive material. The 3D memory structure also includes a base logic die including second multilayer contact pads having a second outer pad composed of the first conductive material. The 3D memory structure further includes hybrid bonding links coupled between the second outer pad of the second multilayer contact pads of the base logic die and the first outer pad of the first multilayer contact pads of the first memory die. The hybrid bonding links are composed of the first conductive material.

A three-dimensional (3D) memory device and a fabricating method thereof are disclosed. The 3D memory device can comprise an array of memory cells. Each memory cell can comprise a capacitor and a vertical transistor. The vertical transistor can comprise a semiconductor body extending in a vertical direction and in contact with the capacitor, and a three-sided gate structure surrounding the semiconductor body from three lateral directions. The 3D memory device can further comprise a memory controller configured to control the array of memory cells.

Embodiments of the present disclosure relate to hybrid parity for three-dimensional memory. Various examples are directed to systems and methods involving a memory device that includes a memory array of a number of memory cells arranged in a number of pages, a number of rows, and a number of columns. Each respective memory cell of the number of memory cells may be a column of the number of columns, a row of the number of rows, and a portion of a page of the number of pages. A first column of the number of columns may be electrically coupled to store parity data for a first portion of the number of pages and column redundancy data for a second portion of the number of pages.

A three-dimensional (3D) memory includes a first semiconductor structure having a 3D memory array, wherein the 3D memory array includes a plurality of memory planes, and a second semiconductor structure having a plurality of page buffer circuits, wherein each memory plane has a plurality of bit lines oriented in a bit line direction, a memory-plane-boundary, and a fixed location on the first semiconductor structure, each page buffer circuit has a page-buffer-circuit-boundary, the first semiconductor structure and the second semiconductor structure are bonded to each other in a face-to-face orientation, and a first memory-plane-boundary of a first memory plane, and a first page-buffer-circuit-boundary of a first page buffer circuit, are vertically aligned with each other such that a first portion of the first page-buffer-circuit-boundary is offset from the first memory-plane-boundary in the bit line direction so as to be non-overlapping with an area defined by the first memory-plane-boundary.

The present invention discloses a wordline bridge in a 3D memory array. The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number of wordline steps in a 3D memory array. A device may include a memory array having memory cells. The memory array includes a first block of pages of memory cells in a first tile and a second block of pages of memory cells in a second tile. The device may also include a polysilicon wordline bridge that couples a first wordline of the first block to a second wordline of the second block for coupling the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of the polysilicon connecting the first tile to the second tile.

A memory unit, a 3D memory and its manufacturing method, and an electronic device, which relate to the semiconductor technical field, include a first transistor and a second transistor disposed on a substrate (1), the first transistor including a first gate electrode (11), a first electrode (33), a second electrode (34), and a first semiconductor layer (6) disposed on the substrate, the second transistor including a third electrode (51), a fourth electrode (52) disposed on the substrate (1), a second gate electrode (12) extending along a direction perpendicular to the substrate (1), and a second semiconductor layer (9) surrounding a sidewall of the second gate electrode (12), the second semiconductor layer (9) including a second source contact region (91) and a second drain contact region (92) disposed at an interval, and a channel between the second source contact region (91) and the second drain contact region (92) being a horizontal channel.

Provided is a three-dimensional (3D) memory device including: a substrate, a stack structure, and a vertical channel pillar. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately. The vertical channel pillar penetrates through the stack structure. The vertical channel pillar includes a first source / drain pillar and a channel layer laterally surrounding the first source / drain pillar. The first source / drain pillar includes a first buffer pillar and a first semiconductor layer having a first conductivity type wrapping the first buffer pillar. The channel layer includes a polysilicon layer having a second conductivity type different from the first conductivity type. In some embodiments, the 3D memory device may be, but is not limited to, a AND flash memory.

A three-dimensional (3D) memory device is disclosed. The 3D memory device includes a memory stack, a semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack, and a source contact above the memory stack and in contact with the semiconductor layer. A semiconductor plug, in contact with the semiconductor layer, surrounds an end of one of the channel structures. The source contact is electrically connected with the one of the channel structures. At least a portion of the source contact is buried within the semiconductor layer.