276 results about "3d memory" patented technology

A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.

Described are memory devices having an array region and an extension region adjacent the array region. The array region includes at least two unit cells stacked vertically. The extension region includes a memory stack and a plurality of word line contacts. The memory stack comprises alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. The plurality of word line contacts extend through the memory stack to the at least one conductive layer. Each of the plurality of word line contacts have a height that is different than the height of an adjacent word line contact. Each of the plurality of word line contacts has a metallization layer on the top surface. Methods of forming a memory device are described.

A transistor, a 3D memory and a manufacturing method therefor, and an electronic device are provided in the present application. The 3D memory includes a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, and a word line. A memory cell includes a transistor which includes a source and a drain, a gate extending in the direction perpendicular to the substrate, a semiconductor layer surrounding a sidewall of the gate. The semiconductor layer includes a source contact region and a drain contact region arranged at intervals. A channel between the source contact region and the drain contact region is a horizontal channel, and the word line extends in the direction perpendicular to the substrate and penetrates through the memory cells of different layers.

A memory, a dynamic random access memory, and an electronic device are provided. The memory may be a 3D memory, and includes: a substrate; a plurality of memory cell columns distributed in a first direction perpendicular to the substrate, wherein each memory cell column includes a plurality of memory cell stacked in the first direction; each memory cell includes a transistor and a capacitor; the transistor comprises a semiconductor layer and a gate, and the semiconductor layer includes a first semiconductor layer and a cylindrical second semiconductor layer arranged on the sidewall of the first semiconductor layer. Other structures of the transistor and capacitor have the same definition as those in the description.

Technology for driving word lines in 3D memory. Even numbered word lines in a 3D memory are biased from one end of the word lines and odd numbered word lines in the 3D memory are biased from the other end of the word lines. The word lines may reside in a stack of alternating conductive and dielectric layers, with the conductive layers serving as the word lines as well as select lines. The ends of the word lines on one side of the stack may form a first staircase and the ends of the word lines on an opposite side of the stack may form a second staircase. A first set of word line driver transistors connect to the even numbered word lines at the first staircase and a second set of word line driver transistors connect to the odd numbered word lines at the second staircase.

Examples are disclosed that relate to etching features in a layer of silicon oxide doped with an etch rate-modifying dopant. One example provides a method of performing a memory device fabrication process. The method comprises placing a substrate in a processing chamber of a processing tool, the substrate comprising a first structure comprising alternating layers in a mold stack for a 3D memory structure, and the substrate also comprising a second structure comprising a silicon oxide layer doped with an etch rate-modifying dopant. The method further comprises controlling the processing tool to perform an etching cycle comprising etching at least a portion of a channel hole in the first structure of the substrate and at least a portion of a hole in the second structure of the substrate.

A three-dimensional (3D) memory structure includes a memory array formed on a side of a substrate, a far-back-end-of-line (FBEOL) structure formed on the memory array, and a back-end-of-line (BEOL) structure formed on another side of the substrate opposite the side on which the memory array and the BEOL structure are formed. Methodologies to fabricate the 3D memory structure are also disclosed and include forming the memory array on the substrate, forming the FBEOL on the memory array, flipping the substrate, and forming the BEOL on the opposite side of the substrate. Alternative 3D memory structures and fabrication methodologies are also disclosed.

Provided are a three-dimensional (3D) memory device using a self-selecting memory and / or an operation method of the 3D memory device. The 3D memory device may include a plurality of memory cells arranged in three dimensions on a substrate. Each of the plurality of memory cells may include a transistor and a self-selecting memory layer connected in series. The transistor may include a channel layer and the channel layer may be parallel to a surface of the substrate. The self-selecting memory layer may include a chalcogenide-based material having Ovonic threshold switching characteristics. The self-selecting memory layer may be configured to have a threshold voltage change according to a polarity and an intensity of an applied voltage.

To provide a structure and a method for forming a three-dimensional (3D) memory device.SOLUTION: In one example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of staircases each having at least a laterally extending conductor / dielectric pair. The staircase region includes a drain select gate (DSG) cut structure extending along the lateral and vertical directions, and a plurality of support structures extending within the DSG structure along the vertical direction. At least one dimension along a lateral direction of the support structure is greater than a dimension along a second lateral direction perpendicular to the lateral direction.SELECTED DRAWING: Figure 1C

A method includes obtaining a substrate structure of a three-dimensional (3D) memory device, forming a barrier layer comprising a high-k dielectric material on the substrate structure, and forming a word line comprising molybdenum for the 3D memory device on the barrier layer using an atomic layer deposition (ALD) process.

A 3D memory device includes a memory stack having alternating stacked conductive layers and stacked dielectric layers, a semiconductor layer, and a channel structure extending vertically through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel. A first doping concentration of a portion of the semiconductor channel in the first portion of the channel structure is greater than a second doping concentration of a portion of the semiconductor channel in the second portion of the channel structure.

This invention provides a wafer matching method and apparatus, a fabrication method, an electronic device, and a storage medium. The wafer matching method includes: obtaining a set of influence factors for multiple first wafers and multiple second wafers; obtaining a set of principal component factors by dimensionality reduction based on the set of influence factors; determining the degree of matching between each first wafer and each second wafer based on the set of principal component factors; and selecting a second wafer that matches the first wafer from the multiple second wafers based on the degree of matching. This invention not only reduces the workload in determining the degree of matching between wafers by using the set of principal component factors to represent all influence factors, thus improving the production efficiency of 3D memory, but also ensures optimal and stable matching between the first and second wafers by matching the degree of matching, thereby improving the reliability of 3D memory devices fabricated by bonding processes.

Provided are a semiconductor structure which may be used in a 3D AND flash memory and a manufacturing method thereof. The semiconductor structure includes a substrate having a memory device region including memory array and staircase regions and a peripheral region, a circuit structure layer and a first conductive layer sequentially on the circuit structure layer, a stacked structure including second conductive layers and insulating layers and having a staircase profile on the first conductive layer in the memory device region, an oxide layer on the first conductive layer, an insulating wall in the oxide layer, and dummy pillars in the peripheral and staircase regions. The insulating wall penetrates the first conductive layer and surrounds the stacked structure. Each dummy pillar in the peripheral region penetrates the oxide layer and the first conductive layer. Each dummy pillar in the staircase region penetrates the stacked structure and the first conductive layer.

A 3D memory device includes a plurality of mats that each include a memory array stacked over logic circuitry supporting operations of the memory array. The logic circuitry include a local column decoder under the memory array for selecting one or more local column select lines associated with a memory operation. The logic circuitry furthermore includes one or more selectable global array data bus redrivers for receiving global data signals from a set of global data signal buses, selecting one of the global data signal buses, and amplifying signals between the selected global data signal bus and a local data signal bus that communicates the data signals to and from the memory array. The 3D memory device supports concurrent sub-page accesses which may be interleaved for efficient memory operations.

Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. A disclosed 3D memory device can comprise an alternating conductive / dielectric stack on a substrate, a plurality of channel structures in the alternating conductive / dielectric stack, and a plurality of gate line slit (GLS) structures in the alternating conductive / dielectric stack. Each GLS structure can include a plurality of first type GLS portions penetrating the alternating conductive / dielectric stack, and a plurality of second type GLS portions in an upper portion of the alternating conductive / dielectric stack.

A three-dimensional 3D memory device includes a substrate, a peripheral device disposed on the substrate, a memory stack disposed above the peripheral device and including a plurality of conductor / dielectric layer pairs, and a plurality of memory strings, each of the memory strings extending through the memory stack. The peripheral device includes at least a transistor disposed on the substrate. The transistor includes a gate stack. The gate stack of the transistor includes a staircase structure, and an operational voltage of the transistor is above 5 volts.

The present application provides a three-dimensional memory and a method for manufacturing the same. The method includes: forming a stacked structure including alternately stacked insulating layers and sacrificial layers on a substrate, and forming a channel hole penetrating the stacked structure; etching a part of the sacrificial layer through the channel hole to form a first groove; forming a first filling layer on the inner walls of the channel hole and the first groove, and forming a second filling layer on the first filling layer in the first groove; and performing an oxidation treatment on the part of the first filling layer not covered by the second filling layer to form a plurality of oxidation portions.

Methods for input / output voltage training of a three-dimensional (3D) memory device is disclosed. The method can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.

A 3D memory device including a stacked structure, a first group of channel structures and a second group of channel structures, a partition structure and at least one support structure is provided. The stacked structure includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A top surface of the stacked structure is parallel to a plane defined by a first direction and a second direction. The first group of channel structures and the second group of channel structures penetrate the stacked structure and are arranged along a first direction. The partition structure includes a plurality of discrete partition structures and is disposed between the first group of channel structures and the second group of channel structures. The plurality of discrete partition structures are arranged along the second direction and penetrate the stacked structure. At least one support structure is disposed between the adjacent discrete partition structures. The 3D memory device is a 3D NAND flash memory device with high capacity and performance.

A three-dimensional (3D) memory device includes a stacked structure having interleaved conductive and dielectric layers, and a channel structure extending through the stacked structure in a first direction. The channel structure contacts the source electrode of the 3D memory device at its bottom. The channel structure includes a semiconductor channel and a memory film over the semiconductor channel. The memory film includes a first angular structure, and a first diameter of the memory film at its bottom below the first angular structure is smaller than a second diameter of the memory film at its upper portion above the first angular structure.

A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. At least one DRAM cell unit includes a transistor and a capacitor. The capacitor includes a first metal layer, a capacitor dielectric layer positioned on the first metal layer, and a second metal layer positioned on the capacitor dielectric layer. The capacitor is elongated in a horizontal direction parallel to the working surface of the substrate. The second metal layer has a first end and a second end in the horizontal direction. The transistor includes a channel structure, and a gate structure disposed all around the channel structure. The first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor.

The application discloses a 3D memory device and a manufacturing method thereof. The 3D memory device comprises a chip storage area, the chip storage area comprises: a stack structure on a semiconductor substrate; a plurality of gate line gaps penetrating through the stack structure, part of the gate line gaps divide the chip storage area into a plurality of block storage areas, the plurality of gate line gaps are arranged along a first direction, and a plurality of channel columns penetrating through the stack structure are arranged between adjacent gate line gaps, the chip storage area comprises a central area and at least one edge area arranged along the first direction, and the minimum distance between at least one gate line gap and its adjacent channel column in the at least one edge area is greater than the minimum distance between at least one gate line gap and its adjacent channel column in the central area. By increasing the minimum distance between the gate line gap and its adjacent channel column in the edge area, the influence of stress and load effect on the 3D NAND device is avoided, and the low reliability and low yield of the 3D NAND device are avoided.

Methods for, apparatuses with and vertical 3D memory devices are described. A vertical 3D memory device may comprise: a plurality of contacts associated with a plurality of digit lines and extending through a substrate; a plurality of word line plates separated from one another by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a first dielectric material positioned between the first plurality and the second plurality of word line plates, the first dielectric material extending in a serpentine shape over the substrate; a conformal material positioned between the first dielectric material and the first and second plurality of word line plates, respectively; a plurality of spacers; a plurality of pillars coupled with the plurality of contacts; and a plurality of storage elements each comprising chalcogenide material positioned in a recess.

The present invention relates to the technical field of memory fabrication, and provides a method for doping a side wall of a 3D memory device. The main steps thereof comprise: performing a deposition treatment on the side wall of a 3D memory device; performing an annealing treatment by means of a longwave-light annealing process or a rapid thermal annealing process; and etching away a capping layer portion by means of a longitudinal etching process for the anisotropic selective specific etching of SiO2, and cyclically repeating the above steps of deposition, annealing and etching a predetermined number of times to finish the doping of the side wall. The present invention can complete the doping of the side wall of a deep trench of a 3D memory device at a deep-submicron-scale or nanometer-scale depth, and can form a buffer layer with an accurately controllable depth or concentration.

Three-dimensional (3D) memory devices and methods of forming the same are disclosed. In a particular aspect, a 3D memory device includes a first semiconductor assembly, a second semiconductor assembly, and an inter-assembly bonding layer between the first semiconductor assembly and the second semiconductor assembly. The first semiconductor assembly includes a first array structure and a first peripheral structure. The first array structure includes a first memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The first peripheral structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor assembly includes a second array structure and a second peripheral structure. The second array structure includes a second memory stack having a plurality of interleaved stacked conductive layers and stacked dielectric layers. The second peripheral structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer above and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts are distributed below and in contact with the source line mesh.

One aspect of this description relates to a semiconductor device. In some embodiments, the semiconductor device includes a first drain / source structure extending in a first direction, a second drain / source structure extending the first direction and spaced from the first drain / source structure in a second direction perpendicular to the first direction, a third drain / source structure extending in the first direction and spaced from the second drain / source structure in the second direction, a first bit line disposed over the first drain / source structure in the first direction, a common select line that includes a portion disposed over the second drain / source structure in the first direction, a second bit line disposed over the third drain / source structure in the first direction, and a charge storage layer coupled to at least a first sidewall of each of the first drain / source structure, the second drain / source structure, and the third drain / source structure.

A three-dimensional (3D) memory device includes a memory stack including a memory block. The memory block includes a memory array structures and a staircase structure in a first lateral direction, and fingers in a second lateral direction perpendicular to the first lateral direction. The fingers include a first finger and a second finger. The 3D memory device also includes a source-select-gate (SSG) cut structure extending through a portion of the memory stack and between the first finger and the second finger. The staircase structure includes a first staircase connected to first memory cells in the first finger and a second staircase connected to second memory cells in the second finger.

The invention discloses a vector database based on three-dimensional storage calculation. A processing circuit, namely a vector distance calculation circuit (VDCC), sinks to a storage array, namely the bottommost layer of a storage circuit. By greatly reducing the granularity and using large-scale parallel computing, accurate and rapid violent search can be realized for the high-dimensional giant vector database.