Memory Architecture of 3D Array With Diode in Memory String

Abstract

Various embodiments are directed to 3D memory arrays that lack a select line and devices controlled by the select line between one of the source line and the bit line, and the memory cells. Diodes between the other of source line and the bit line, and the memory cells provide needed isolation from the memory cells.

Description

REFERENCE TO RELATED APPLICATION[0001]This application claims the benefit of U.S. Provisional Patent Application No. 61 / 500,484 filed 23 Jun. 2011, which is incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.[0004]2. Description of Related Art[0005]As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been looking to techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin film transistor techniques are applied to charge trapping memory technologies in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. ...

AI Technical Summary

Benefits of technology

[0012]Diodes positioned by the source line end of the NAND string perform electrical isolation between the source line end of the NAND string and the source line. With the diodes performing such electrical isolation, the GSL ground select line-controlled transistors are not required to selectively isolate the source line end of the NAND string from the source line.

Problems solved by technology

So, although the benefits of higher density are achieved using 3D arrays, the higher manufacturing costs limit the use of the technology.

Also, there is a limit in the number of control gates that can be layered in this way, determined by such factors as the conductivity of the vertical channel, program and erase processes that are used and so on.

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