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Method for verifying Cache coherence protocol and multi-core processor system

A verification method and multi-processor technology on a chip, which is applied in the field of multi-core processor system and Cache consistency protocol verification, can solve problems such as lack of universality, and achieve the effect of accurate behavior monitoring

Active Publication Date: 2013-01-16
JIANGNAN INST OF COMPUTING TECH
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  • Application Information

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Problems solved by technology

[0005] However, in the prior art, the processing process of the Cache coherence protocol on the multi-core processor is closely related to the processor structure, and the verification technology of the Cache coherence protocol is closely related to the content of the Cache coherence protocol, which is not universal

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  • Method for verifying Cache coherence protocol and multi-core processor system
  • Method for verifying Cache coherence protocol and multi-core processor system
  • Method for verifying Cache coherence protocol and multi-core processor system

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Embodiment Construction

[0025] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

[0026] The Cache consistency protocol verification method of the present invention includes: setting multiple queues in the monitor, and each queue includes multiple units for recording all requests that have not been processed completely; entering all address-related requests according to their consistency The order of the processing components is stored sequentially within the cells of the same queue; use each cell to independently track the behavior status of the recorded requests. Thus, according to the recorded request type and the sequence of port signals, it is possible to accurately judge the lifetime of a request in consistent processing and whether the processing is correct or not.

[0027] The method for verifying the Cache consistenc...

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Abstract

The invention provides a method for verifying a Cache coherence protocol and a multi-core processor system. The method for verifying the Cache coherence protocol comprises the following steps that: a plurality of queues are arranged in a monitor, every queue comprises a plurality of units, the units are used for recording all primary requests which are not processed completely, all the requests which are relevant to addresses are orderly stored in the units of the same queue according to the sequence in which the requests enter a coherence processing element, and every unit is used for tracking the performance status of recorded requests independently. According to the characteristic that the method for verifying the Cache coherence protocol based on the monitor in the invention can process the requests relevant to the memorized and accessed addresses in sequence according to the Cache coherence protocol, the monitor is used for monitoring the protocol-level behavior of the Cache coherence processing element accurately, and the behavior of every request package can be monitored accurately. Through adjusting the content in the monitor, the method for verifying the Cache coherence protocol is suitable for verifying various coherence protocols.

Description

technical field [0001] The present invention relates to the field of computer technology; more specifically, the present invention relates to a Cache consistency protocol verification method; in addition, the present invention also relates to a multi-core processor system adopting the Cache consistency protocol verification method. Background technique [0002] With the rapid development of semiconductor manufacturing technology, the main frequency of single-core processors has gradually approached the limit. A Processor, CMP). [0003] In CMP, the sharing of a single memory space by multiple processor cores makes the contradiction between the speed gap between the processor and the main memory more prominent. Therefore, the CMP design must use a multi-level cache (Cache). to alleviate this contradiction. The CMP system must solve the Cache consistency problem and the consistency verification problem caused by it. What kind of Cache consistency model and its verification ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/44G06F15/167
Inventor 卢宏生王梦嘉郑卫华韩娇张清波陈彦庭唐勇
Owner JIANGNAN INST OF COMPUTING TECH
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