279 results about "State diagram" patented technology

Systems and methods are provided for the design, development and execution of a graphical user interface using a state machine based programming paradigm integrated with a componentized graphical user interface. The present invention generates a graphical state machine representation of the graphical user interface including states for elements of the graphical user interface and any events associated with these elements. The state diagram model provides a graphical structure for handling events associated with the graphical user interface, such as events generated by inputs provided by a user via a graphical user interface element. Furthermore, functionality for the graphical user interface, such as underlying control structure, state management, and event processing can be implemented with a high level textual programming language integrated with the graphical state machine.

System and method for programmatically generating a graphical program in response to state diagram information. The state diagram information specifies a plurality of states and state transitions. A graphical program generation program (GPG program), receives the state diagram information and automatically, i.e., programmatically, generates a graphical program (or graphical program portion) based on the state diagram information. The GPG program automatically includes graphical source code in a block diagram of the graphical program, which serves as a framework of the states specified by the state diagram information and the state transitions, with various “placeholders” or “containers” enabling the user to easily fill in the graphical program with source code specifying execution instructions for each state and Boolean conditions for each state transition. The specific graphical source code automatically generated depends on programming features supported by a particular graphical programming development environment with which the graphical program is associated.

An ultrasound system that has transmit and receive circuitry that, pursuant to a plurality of image settings, transmits ultrasound signals into a patient, receives echoes from a patient and outputs a signal representative of the echo. Control circuitry is provided that sequentially adjusts the image settings so as to cause the transmit and receive circuitry to have a sequence of imaging configurations during an ultrasound imaging study. A memory may be provided that stores a plurality of state diagrams, each defining a sequence of imaging configurations for a particular imaging study, which are accessible by the control circuitry, wherein the control circuitry accesses a selected state diagram to conduct an imaging study. Such a system is particularly useful for imaging studies that utilize contrast agents.

A method of displaying the probabilities associated with a Markov model as a series of interactive plots is disclosed. Three dimensions of probability data associated with a Markov model are presented to a user in a concise manner. Heat maps are used to display probability data from a Markov model so that the user can identify and understand hidden patterns and information in the data such as state and emission transitions which are not possible to see with conventional state diagram plots.

The invention relates to a deep learning based intelligent skin disease auxiliary diagnosis system, which comprises a classifier training unit, a language model unit and an intelligent auxiliary diagnosis unit. The intelligent auxiliary diagnosis unit comprises an image acquisition module, a voice interrogation module, a voice recognition and keyword extraction module, a probability classificationmodel, a RNN condition analysis module and a fusion classifier. The classifier training unit comprises a state diagram training set under a dermatoscope, a state standard database under skin lesion and dermatoscope, a CNN network convolution module and a sampling and classifying module. The language model unit comprises a medical term standard library, a RNN questioning management module, a RNN chief complaint management module and a skin disease medical knowledge base. The auxiliary diagnosis system has advantages that by deep learning for classifying skin lesion images, probable results areinferred, then a pre-installed dermatoscope image and histodiagnosis tag database is retrieved for doctors' reference, and accordingly accuracy in skin disease diagnosis can be greatly improved.

The invention discloses a network security situation awareness model and method based on an attack graph. The model comprises a data preprocessing module, an attack feature library construction module, an attack state identification module, a security situation evaluation module and a security situation prediction module. The method comprises: firstly, collecting data sets of different sources, and obtaining asset vulnerability threat data and asset attack threat data after preprocessing; further analyzing and training by utilizing the asset attack threat data and the principal component dataof the attack information, and establishing an attack feature library; matching the attack portrait, and determining the attack state of the current equipment; then, calculating a security situation value of the whole network by utilizing the asset attack threat data; and finally, predicting the next attack state through the attack and defense game matrix of the attack state diagram so as to predict the network security situation. A good situation awareness effect and a network security situation evaluation and prediction function are realized, and the model and the method have relatively goodpracticability, high efficiency and expansibility.

Hierarchical state diagrams are reflected in a tree structure with the initial state of the diagram represented as the parent node, intermediate states represented as intermediate levels of the hierarchy, and final states represented as the lowest level in the hierarchy. Information on the modification(s) on a child or subsequent level is transferred to the parent node. Such information includes quantifying and displaying of the modification(s). Accordingly, content and extent of any modifications to the diagram can be viewed at the parent node without requiring review of different levels in the hierarchy to view modifications to the state and / or transition in such levels.

Systems and methods are provided for a scheme and mechanism for performing static analysis of a sample time aware state diagram model to compute and propagate multiple samples rates associated with the state diagram model. A graphical intermediate representation of the state diagram model, such as a directed graph or control flow graph, is used to determine how the multiple sample rates are propagated via elements of the state diagram model. The graph provides a static representation of the control of flow, including alternative and / or conditional flow paths, of the state diagram model. The present invention determines the propagation of sample rates via analysis and traversal of the intermediate representation. By using the techniques of the present invention, a state diagram model may provide multiple sample rate outputs, such as by function calls and output signals to a graphical model, such as a model representing a dynamic system.

A ballast controller integrated circuit which executes a specific set of instructions via an integrated state diagram architecture to control a fluorescent lamp or high intensity discharge lamp and protect the ballast. The state diagram architecture controls powering up and down of the IC and the half-bridge circuit driven by the IC, preheating and striking of the lamp, running of the lamp, sensing for numerous possible fault conditions, and recovering from these fault conditions based on the normal maintenance of a lamp, while requiring fewer internal and external components than previous electronic ballasts.

A node (101, FIG. 1), within a networked computer system (100), is capable of supporting communications with other nodes relating to operating multiple application instances in a master-slave configuration. The node initiates (602, FIG. 6) and maintains (FIGS. 7, 8) a state diagram (FIG. 2) for each application instance currently running in the master-slave configuration on the node or the other nodes. In addition, the node listens for new application instances that are discovered on the node or on the other nodes. The nodes can be interconnected using multiple networks (104, FIG. 1), and redundant messages received by the node can be ignored (FIG. 11), if those redundant messages would adversely affect maintenance of the state diagram for an application instance. When a node determines that it should no longer operate as a master for an application instance, the node can initiate a resignation process (FIG. 4), during which another node will attempt to become the master for the application instance.

Based on software developed with use-cases, a suite of metrics for the Product / Process (PP) complexity of software systems as well the PP complexity of each stage in the software development process—analysis, design, and testing—is provided. The metrics suite is important for software quality assurance—Validation and Verification (V&V) as well as for understanding new complexities brought into software development by new technologies. The metrics can be collected based on the two most important documents of use-case software development—scenario diagrams and state diagrams. All metrics are CASE tool computable. Thus, each iterative or incremental development process can be quantitatively measured and compared without incurring extra cost or load on the project team. Efficiency metrics for implementation and test stages, normalization rules and logic-metrics for business tables are also presented. A three-level software visualization approach may have impact on graphical programming or direct transformation.

The present invention provides a state diagramming environment in a computing device that enables the conversion of a state diagram into a hardware description language. To achieve this conversion, the present invention generates an intermediate representation of the state diagram. The intermediate representation is checked against a set of predefined restrictions for compliance. The state diagramming environment converts the intermediate representation of the state diagram into a hardware description language, such as VHDL or Verilog.

System and method for graphically specifying hardware timing and triggering. A diagram is displayed graphically representing user-configurable timing and triggering components of a device, e.g., icons and signal paths representing operational relationships between the components, where timing and triggering for the device is determined by timing and triggering attributes. The diagram receives user input specifying one or more of the timing and triggering attributes, e.g., parameters, signal routes, etc., and the diagram modified, e.g., graphically configured, in accordance with the specified attributes, where the diagram represents configuration of the user-configurable timing and triggering components. Dependent attributes are programmatically computed based on the specified attributes. The specified attributes are stored and are usable to configure timing and triggering for the device. Program code for configuring the device may be generated based on the diagram. A state diagram may be displayed indicating effects of modifying the diagram on operation of the device.

This invention is directed to a method for use in a state diagramming environment on a computing device. The method includes obtaining a state diagram via the environment and processing a first event for the state diagram via the environment. The method also includes triggering a second event, wherein the triggering is based on the first event. The method further includes broadcasting the second event in a non-blocking fashion that allows the first event to continue being processed.

The invention provides a product source tracing scheme based on PKI (Public Key Infrastructure) and two-dimensional codes. The credible two-dimensional codes can be printed at the outer side of a package of each layer of a product by a manufacturer. In each product circulation loop, a product can be verified through the two-dimensional codes. Data of all the circulation loops can be sent to a product source tracing center. The manufacturer, a dealer and a user only need to scan the two-dimensional codes on the product to see a tree state diagram of the product in the entire circulation process. The product source tracing scheme can be used for providing a simple and rapid management manner for product source tracing. Shown by a picture, the scheme at least consists of a product source tracing center module, a CA (Certificate Authority) module, a two-dimensional code generation module and a two-dimensional code verification module.

A system and method of exposing debugging information in a graphical modeling and execution environment is disclosed. The present invention allows a user to view debugging information in the same window as the graphical view of the model being executed. Debugging data is associated with relevant components of the model displayed in the graphical view. A separate execution list view shows the methods called during the execution of the block diagram in the current time step up until the current point in execution. User-set breakpoints and conditional breakpoints may be set in both the model view and the execution list view. Values may be obtained for all of the displayed methods. The debugging tool may be implemented by using it in conjunction with a graphical modeling and execution environment, such as a block diagram environment or state diagram environment.

A system and method for contextualizing operating procedures are provided. A set of procedures is provided, each including text describing user actions which are to be performed on a physical device to implement the procedure. A device model refers to components of the device on which user actions are performable and provides state charts which link an action performable on the respective component with states assumed by it. The text of each procedure is segmented to form a sequence of steps. Each step includes an action to be performed on one of the components of the device that is referred to in the device model. When a request for one of the procedures is received, the corresponding sequence of instruction steps is retrieved. A current one of the instruction steps is contextualized, based on device data received from the device and the state chart of the respective component.

A method of providing multi-instantiable state templates to a statechart environment is discussed. The method includes the step of providing a graphical definition of an independent state machine object belonging to a statechart. The method further includes the step of instantiating a first instance and a second instance of the independent state machine object in the statechart. The method additionally includes the steps of starting execution of the first instance of the independent state machine object and then stopping execution of the first instance of the state machine object. Additionally, the method includes the step of starting the execution of the second instance of the independent state machine object in the state diagram.

A positive electrode active material for a lithium secondary cell having a high energy density and excellent in charging / discharging cycle performance, and a lithium secondary cell having a high energy density and excellent in charging / discharging cycle performance are disclosed. A positive electrode active material for a lithium secondary cell is characterized in that the composition of the active material is LixMnaNibCocO2 where a, b, and c are values of a point a, b, c on a side of or inside a quadrilateral ABCD having vertexes A (0.5, 0.5, 0), B (0.55, 0.45, 0,) C (0.55, 0.15, 0.30), and D (0.15, 0.15, 0.7) on a ternary state diagram showing the relationship among a, b, and c, and satisfy the expressions 0.95 H01M 4 / 48 H01M 4 / 58 H01M 4 / 02 H01M 10 / 40 C01G 53 / 00 3 36 2 2002 / 11 / 21 1723576 2006 / 1 / 18 100353596 2007 / 12 / 5 2007 / 12 / 5 2007 / 12 / 5 Yuasa Battery Co., Ltd. Japan Shiozaki Ryuji Fujii Akihiro Okabe Kazuya Nukuda Toshiyuki ding xianglan 11127 San You Patent Agency No.201 Entrance 1, Building 13, the East of Jinmenli, Haidian District, Beijing 100088 Japan 2001 / 11 / 22 358017 / 2001 2004 / 3 / 31 PCT / JP2002 / 012171 2002 / 11 / 21 WO2003 / 044881 2003 / 5 / 30 Japanese

The present invention provides a user of a state diagramming environment with the ability to specify if the user wants to develop a Moore machine or a Mealy machine. To achieve this, a set of predefined requirements is provided that restricts the state diagram semantics to either semantics of a Moore or Mealy machine. When a user provides a state diagram that does not conform to the set of requirements, the state diagram is identified as non-conforming and the user is notified of the non-conformance. The user is given information describing what aspects of the state diagram do not conform, thereby, allowing the user to quickly identify any errors that have been made. As a result of the present invention, the burden placed on the user is reduced and the time spent debugging is minimized.

The invention includes a state engine system, the system including: a CPU; a memory operatively connected to the CPU, the memory containing a program adapted to be executed by the CPU and the CPU and memory cooperatively adapted for managing a plurality of objects stored in a database, whose behavior can be modeled by means of a state diagram reacting on external events which occur in a non-deterministic order. The program contained in the memory includes a code segment embodied on a computer-readable medium configured and adapted for creating, storing and maintaining state diagram templates in a database, the database including all states available for the object, the possible state transitions, the events which cause state transitions, and the actions which occur upon state transitions: where there is at least one event causing each state transition; and where the actions which occur upon a state transition is dependent upon the event that caused the transition; a code segment embodied on a computer-readable medium configured and adapted for creating a new instance of a state diagram for each new object and maintaining its current state in the running state diagram; a code segment embodied on a computer-readable medium configured and adapted for receiving notification of an event and applying it to the relevant running state diagram; a code segment embodied on a computer-readable medium configured and adapted for causing a state transition upon receiving notification of a event; and a code segment embodied on a computer-readable medium configured and adapted for causing the occurrence of one or more pre-determined actions triggered by a state transition, where one of the pre-determined actions is the initiation of a timer, where the timer is configured to cause an event to occur after a pre-determined time.

A method for generating procedures includes receiving a log of a troubleshooting session. The log includes device data including a sequence of detected operations performed on the device causing respective components to change states. Steps of a candidate operating procedure are generated, based on the log, each corresponding to one of the detected operations. Missing steps may be identified, based on state charts and / or stored operability constraints for the device. The candidate operating procedure is compared with existing operating procedures stored in a knowledge base for the device to identify at least one existing operating procedure which includes steps which match at least some of the steps of the candidate operating procedure and, based on the identified at least one existing operating procedure, generating a textual description based on the textual description of the matching steps. The candidate procedure can be presented to an editor for validation.

System and method for graphically specifying hardware timing and triggering. A diagram is displayed graphically representing user-configurable timing and triggering components of a device, e.g., icons and signal paths representing operational relationships between the components, where timing and triggering for the device is determined by timing and triggering attributes. The diagram receives user input specifying one or more of the timing and triggering attributes, e.g., parameters, signal routes, etc., and the diagram modified, e.g., graphically configured, in accordance with the specified attributes, where the diagram represents configuration of the user-configurable timing and triggering components. Dependent attributes are programmatically computed based on the specified attributes. The specified attributes are stored and are usable to configure timing and triggering for the device. Program code for configuring the device may be generated based on the diagram. A state diagram may be displayed indicating effects of modifying the diagram on operation of the device.

The invention discloses a function test system of an automobile body control module. The function test system comprises a junction box which is connected with an automobile function module to be tested, and the junction box is connected with a digital board card which is connected with an industrial personal computer. The invention also discloses a test method by utilizing the system. According to the function test system and the test method, on the aspect of hardware construction, the realization is convenient and rapid, under the premise of ensuring the precision, the cost is lowered, the system is expanded by loading different functions of board cards, and then can be conveniently connected with a device to be tested by the junction box, and on the aspect of test software, the system has the largest characteristics that a state diagram is utilized for generating a test case, the test purpose is realized by traversing the work state of a BCM (Body Control Module), the understanding is convenient, the operation is easy, the test effect is achieved, and when the test case is tested, the automatic batch test can be selected, the singly manual test is conducted, the function consistency can be automatically analyzed and designed in advance, the manual comparison can be conducted to implement sequential analysis, so that the problem can be found and checked conveniently.

The AV system is an AV system comprising a display device and a plurality of AV appliances including an AV appliance having plural functions connected by way of a digital interface, in which the types of plural AV functions, and information of input and output of video signal and audio signal are acquired by way of the digital interface, and icons of plural AV appliances, and the connection state diagram showing the flow of video signal and audio signal are displayed on the display device, and the AV appliances can be operated from the connection state diagram. In this AV system, the connection relation of AV appliances, and the flow of video and audio signals can be recognized intuitively, and the appliances can be operated easily from the television screen.

The invention discloses a built-in test (BIT) modeling simulation method based on a state diagram, belonging to the technical field of test of electronic information. The method comprises the following steps of: step 1, establishing a state diagram model of a tested unit; step 2, establishing a state diagram model of the BIT; step 3, establishing a state diagram model of interference; step 4, establishing a BIT simulation comprehensive model; step 5, performing fault and interference injection and simulation evaluation. The method provides a universal key element template of the BIT based on design characteristics of the BIT, and BIT key element decomposition can be quickly performed according to the template; and the method provides basic modes for state diagram modeling of each element in the BIT, and can perform modeling on common analogue BIT, digital BIT and software BIT. The invention provides a simulative injection method for the fault and the interference, and fault detection and false alarm suppression capability of the BIT can be analyzed through state simulation.

A method for analyzing safety of large-capacity network includes collecting information of each host, network, attacker and attack means in network and carrying out model detection by setting up finite state unit; obtaining state sequence from initial state to safe attribute being violated by detection and finding out conversion condition of state sequence; utilizing said state sequence and conversion condition to plot out a safety-analysis state diagram being used to analyze and evaluate safety of network.

The invention relates to a method for verifying the consistency of a dynamic behavior in a unified modeling language (UML) model and a time-sequence contract. The method is characterized by comprisingthe following steps: modeling according to the UML standard, including generating a UML state diagram and a UML sequence diagram, and then saving the metamodels of the diagrams; mapping the UML statediagram to a PROMELA code for the dynamic behavior of the model; establishing the time-sequence contract of the model to map the UML sequence diagram to an LTL temporal logical formula; utilizing a model verifying tool SPIN to verify the PROMELA code and the LTL temporal logical formula; and analyzing the returned SPIN verifying result. The technical scheme of the invention associates the unifiedmodeling language (UML) and the verifying tool together, solves the problem of model inconsistency arisen in the requirement and design stage of soft engineering and provides an effective basis for the subsequent development of model driving type software.