PCIe interface verification method and verification system

Abstract

The invention discloses a PCIe interface verification method and a PCIe interface verification system, and relates to the technical field of test.According to the PCIe interface verification method, after a PCIe interface is divided into a PCIe controller and a PCIe physical layer, a simulation PCIe controller can be constructed based on programmable hardware resources in a programmable logic device, and the simulation PCIe controller can be constructed in non-programmable hardware resources of the programmable logic device; at least a portion of the physical layer is selected as a simulated PCIe physical layer. After the simulation PCIe controller and the simulation PCIe physical layer are connected, the simulation PCIe controller and the simulation PCIe physical layer can communicate with each other, namely, the combination of the simulation PCIe controller and the simulation PCIe physical layer can be regarded as a simulation PCIe interface. Therefore, prototype verification of the PCIe interface can be realized based on the simulation PCIe interface, so that the problem that prototype verification cannot be performed on the PCIe interface in some technologies is solved.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a PCIe interface verification method and verification system. Background Art

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard that uses high-speed differential signal transmission technology and has the characteristics of high bandwidth, low latency, and scalability. It is a widely used industry standard interface. The use of PCIe interface in integrated circuit design can bring many benefits. For example, it can ensure that the designed integrated circuit is compatible with a large number of devices and motherboards on the market that support PCIe interface, thereby reducing design costs and risks. For example, for high-performance integrated circuits such as central processing units (CPUs) and graphics processing units (GPUs), it is usually necessary to interact with other components such as memory, storage devices, and network interfaces for a large amount of data. The use of PCIe interfaces in these integrated circuits can meet the needs of these integrated circuits for high-speed data transmission.

[0003] Prototyping the PCIe interface in the early stages of integrated circuit design can significantly improve the success rate of integrated circuit tape-out. However, there is currently a lack of effective solutions for prototyping the PCIe interface. Summary of the Invention

[0004] The present application provides a PCIe interface verification method and a PCIe interface verification system to at least solve the problem in the related art that a prototype verification of a PCIe interface cannot be performed.

[0005] The present application provides a PCIe interface verification method, wherein: the PCIe interface verification method includes:

[0006] Divide the PCIe interface into a PCIe controller and a PCIe physical layer, wherein the PCIe controller is used to perform logical operations related to the PCIe protocol, and the PCIe physical layer is used to transmit PCIe signals;

[0007] Building an emulated PCIe controller based on programmable hardware resources in a programmable logic device, and using at least a portion of a physical layer in non-programmable hardware resources of the programmable logic device as an emulated PCIe physical layer;

[0008] Connecting the simulated PCIe controller and the simulated PCIe physical layer to obtain a simulated PCIe interface;

[0009] Based on the simulated PCIe interface, functional verification of the PCIe interface is performed.

[0010] The present application provides a PCIe interface verification system, wherein: the PCIe interface verification system includes:

[0011] A simulated PCIe controller, configured to simulate a PCIe controller in a PCIe interface, wherein the PCIe controller is configured to perform logic operations related to the PCIe protocol and is constructed based on programmable hardware resources in a programmable logic device;

[0012] A simulated PCIe physical layer, used to simulate a PCIe physical layer in the PCIe interface, wherein the PCIe physical layer is used to transmit PCIe signals, and the simulated PCIe physical layer is a non-programmable hardware resource in the programmable logic device;

[0013] The simulated PCIe controller is connected to the simulated PCIe physical layer to obtain a simulated PCIe interface, and the simulated PCIe interface is used for functional verification of the PCIe interface.

[0014] In the technical solutions of some embodiments of the present application, after the PCIe interface is divided into a PCIe controller and a PCIe physical layer, an emulated PCIe controller can be constructed based on the programmable hardware resources in the programmable logic device, and at least part of the physical layer can be selected from the non-programmable hardware resources of the programmable logic device as the emulated PCIe physical layer. After the emulated PCIe controller and the emulated PCIe physical layer are connected, the emulated PCIe controller and the emulated PCIe physical layer can communicate with each other, that is, the combination of the emulated PCIe controller and the emulated PCIe physical layer can be regarded as an emulated PCIe interface. In this way, based on the emulated PCIe interface, prototype verification of the PCIe interface can be achieved, thereby solving the problem that some technologies cannot perform prototype verification on the PCIe interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 A flowchart of a PCIe interface verification method provided in some embodiments of the present application;

[0017] Figure 2A schematic diagram of the connection between multiple simulated PCIe interfaces and an analog controller provided in some embodiments of the present application;

[0018] Figure 3 A module diagram of a PCIe interface verification system provided for some embodiments of the present application. DETAILED DESCRIPTION

[0019] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0020] It should be noted that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating positions or positional relationships, are based on the positions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present application. The terms "mounted", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be internal communication between two elements. The terms "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, where the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes both absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism may be, for example, within 5°; "perpendicular" includes both absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity may also be, for example, within 5°. "Equal" includes both absolute equality and approximate equality, where the acceptable deviation range for approximate equality may be, for example, that the difference between the two is less than or equal to 5% of either. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0021] In this application, prototype verification refers to the process of building a physical model and a real operating environment for the PCIe interface in the integrated circuit in the early stage of the design of the integrated circuit (that is, before the integrated circuit is officially taped out) to verify whether the functions of the PCIe interface can meet expectations. For example, it can be verified whether the functions such as the communication rate, error handling and recovery mechanism of PCIe can meet expectations. By performing prototype verification on the PCIe interface, design defects and potential problems can be discovered and resolved in advance during the design process. In this way, when the integrated circuit is officially taped out, the tape-out success rate of the integrated circuit can be greatly improved, thereby reducing the design cost.

[0022] Currently, some technologies lack effective solutions for prototyping PCIe interfaces. In view of this, the present application provides a PCIe interface verification method that can address the problem of being unable to perform prototype verification on PCIe interfaces in some technologies. The PCIe interface verification method can be applied to programmable logic devices. Programmable logic devices may include, but are not limited to, FPGA (Field-Programmable Gate Array) chips, CPLD (Complex Programmable Logic Device), SoC FPGA (System on Chip Field Programmable Gate Array), etc. Programmable logic devices may include a large number of hardware circuit resources, such as programmable logic units, interconnect resources, and input / output blocks. These hardware circuit resources are highly flexible and programmable. Using hardware description languages ​​to design and configure these hardware circuit resources, various complex hardware circuit modules can be obtained, such as ARM (Advanced RISC Machine) processors, bus interfaces, memory controllers, communication interfaces, and other customized functional circuit modules.

[0023] Based on the PCIe interface design code, a programmable logic device (PLD) configuration file can be generated. Based on the configuration file, the PLD can construct a physical model of the PCIe interface. This physical model allows for prototype verification of the PCIe interface. The physical model refers to the hardware circuitry that implements the PCIe interface functionality, built using the hardware circuit resources within the PLD.

[0024] See also Figure 1 , which is a flow chart of the PCIe interface verification method provided in some embodiments of the present application. Figure 1 The PCIe interface verification method may include the following steps:

[0025] Step S101: Divide the PCIe interface into a PCIe controller and a PCIe physical layer.

[0026] Specifically, the PCIe physical layer, also known as the PHY (Physical Layer), is primarily used to transmit PCIe signals. During PCIe signal transmission, the PCIe physical layer performs operations including, but not limited to, the following:

[0027] 1) Send and receive differential signals on the PCIe link. Differential signals represent data, control information, and clock signals in the PCIe protocol. Differential signals can improve the anti-interference ability of the PCIe link.

[0028] 2) Initialize and train the PCIe link. This includes sending and receiving training sequences and adjusting transmitter and receiver equalization and timing settings to ensure data channel stability and synchronization.

[0029] 3) Generate the clock signal required to transmit the differential signal and extract the clock information from the received differential signal. The clock signal or clock information is used for data synchronization and decoding.

[0030] 4) Encode the transmitted data to increase data redundancy and improve anti-interference capabilities, and decode the received signal to restore the original transmitted data.

[0031] 5) Monitor and manage signal integrity. For example, detect bit errors, frame errors, etc. in the signal and take appropriate measures (such as retransmission, error reporting, etc.) to correct these errors.

[0032] 6) When the PCIe interface supports hot plugging of PCIe devices, it is responsible for detecting the insertion and removal events of PCIe devices and notifying the upper-layer software to perform corresponding processing.

[0033] 7) Support different PCIe link widths (e.g., x1, x4, x8) and speeds (e.g., 5.0GT / s for PCIe2.0, 8.0GT / s for PCIe3.0), and adjust the link width and speed of the PCIe link based on the PCIe configuration and the negotiation results between PCIe devices to match the requirements of PCIe devices and systems.

[0034] 8) Assist the PCIe controller to manage the power of PCIe devices. For example, when a PCIe device enters a low-power state, it can reduce the transmit power or shut down some circuits to reduce power consumption.

[0035] The PCIe controller, also known as the PCIe core logic or PCIe protocol layer, is primarily used to perform logical operations related to the PCIe protocol. These operations include, but are not limited to, the following:

[0036] 1) Protocol processing. Specifically, on the one hand, the PCIe controller can encapsulate the upper layer data into a transaction layer packet (Transaction Layer Packet, TLP), and send the encapsulated transaction layer packet to the PCIe physical layer, or receive and parse the transaction layer packet from the PCIe physical layer to extract data from the transaction layer packet. On the other hand, the PCIe controller can manage the data transmission rate between the PCIe receiver and the PCIe transmitter based on the flow control mechanism, so as to prevent data overflow or loss. On the other hand, the PCIe controller can execute the Error Detection and Correction (EDC) algorithm to detect data errors during data transmission and try to correct these errors. If these errors cannot be corrected, an error report is generated.

[0037] 2) Manage the configuration space. Specifically, the configuration space can include reading and writing configuration registers. These registers can be used to store configuration information. Configuration information may include, but is not limited to, device information of the PCIe device connected to the PCIe interface (such as device identification and device type), the PCIe interface rate and link bandwidth (such as x1, x4, x8, x16, etc.). The PCIe controller can control access to these registers, such as verifying the permissions of devices accessing these registers.

[0038] 3) Process the interrupt message and forward it to the upper-level software for processing.

[0039] 4) Assist the PCIe physical layer in PCIe link management and training, such as participating in the management and monitoring of link status, including but not limited to detecting link failures, performing link reset and retraining, etc.

[0040] 5) Manage hot-swap and plug-and-play of PCIe devices, such as detecting the insertion of new devices and initializing devices. It also supports the dynamic addition and removal of PCIe devices during system operation.

[0041] 6) Perform power management on the PCIe device. For example, in response to a power management request, the system collaborates with the power management controller to convert the power state of the PCIe device from a full power state to a low power state.

[0042] Step S102: constructing an emulated PCIe controller based on the programmable hardware resources in the programmable logic device, and using at least part of the physical layer in the non-programmable hardware resources of the programmable logic device as an emulated PCIe physical layer.

[0043] In this embodiment, the programmable logic device is an FPGA chip. A programmable logic device may include programmable hardware resources and non-programmable hardware resources. Programmable hardware resources refer to hardware resources that can be designed and configured using a hardware description language. Programmable hardware resources generally include:

[0044] 1) Lookup table: A basic unit for implementing logical functions. Designed and configured using a hardware description language, the lookup table can implement various logical operations, such as AND, OR, and XOR.

[0045] 2) Flip-flop: A hardware unit used to store data state. In a programmable logic device, a flip-flop can be configured as a register or latch to hold data between logic operations.

[0046] 3) Programmable interconnects, which connect programmable logic cells within a programmable logic device (PLD) to enable communication between them. Programmable logic cells can be composed of combinations of lookup tables, flip-flops, and other components to implement specific functions.

[0047] 4) I / O blocks, used for interactive input and output interfaces with external devices, such as buffers, multiplexers, and inverters.

[0048] Non-programmable hardware resources are hardware resources that cannot be designed and configured using hardware description languages. These are functional modules embedded in programmable logic devices (PLDs) that cannot be modified at will. However, the functionality provided by these hardware resources can be used directly. Non-programmable hardware resources may include, but are not limited to, fixed logic functional units, power and ground connections, package pins, and internal fixed connections. Fixed logic functional units may include, but are not limited to, one or more physical layers.

[0049] In this embodiment, considering that the programmable logic device (PLD) already has a pre-built physical layer, when constructing a true hardware model of the PCIe interface based on the hardware resources within the PLD, the PCIe interface can be split into a PCIe controller and a PCI physical layer. Then, at least a portion of the physical layer within the PLD can be selected as the simulated PCIe physical layer. This eliminates the need to design and configure the hardware resources within the PLD, significantly reducing workload. This simulated PCIe physical layer can be considered a hardware circuit capable of implementing the functions of the PCIe physical layer, but it is not a true PCIe physical layer.

[0050] Furthermore, a configuration file for a programmable logic device (PLD) can be generated based on the PCIe interface design code. Based on this configuration file, programmable hardware resources can be designed and configured using a hardware description language (HDL), resulting in a simulated PCIe controller. This simulated PCIe controller can be considered a hardware circuit capable of implementing the PCIe controller functionality within an integrated circuit, but it is not a true PCIe controller.

[0051] Step S103: Connect the simulated PCIe controller and the simulated PCIe physical layer to obtain a simulated PCIe interface.

[0052] In this embodiment, a hardware description language can be used to design and configure the programmable hardware resources in the programmable logic device to obtain a simulated high-speed interface (such as a simulated high-speed serial interface, a high-speed connector). Among them, similar to the simulated PCIe controller and the simulated PCIe physical layer, the simulated high-speed interface can also be regarded as a hardware circuit that can realize the high-speed interface function, but it is not a real high-speed interface. The simulated high-speed interface can be used to connect the simulated PCIe controller and the simulated PCIe physical layer. In this way, the simulated PCIe controller and the simulated PCIe physical layer can communicate with each other and simulate the functions of the PCIe interface, that is, the simulated PCIe controller and the simulated PCIe physical layer can be combined into a simulated PCIe interface.

[0053] Of course, it is understandable that if the non-programmable hardware resources of the programmable logic device include a high-speed interface, the high-speed interface in the non-programmable hardware resources can also be used to connect the simulated PCIe controller and the simulated PCIe physical layer, and this application does not impose any restrictions on this.

[0054] Step S104: Performing functional verification of the PCIe interface based on the simulated PCIe interface.

[0055] Specifically, because the simulated PCIe controller is built based on the design code of the PCIe interface, the simulated PCIe controller can operate according to the design of the integrated circuit. That is, if the design of the integrated circuit is correct, the operation of the simulated PCIe controller can meet expectations. If there is a problem with the design of the integrated circuit, the operation of the simulated PCIe controller may not meet expectations. For example, after configuring the link bandwidth to x4 in the register of the simulated PCIe interface, if the simulated PCIe interface is used to transmit data, the simulated PCIe interface will transmit data according to the link bandwidth of x4, indicating that the design of the integrated circuit is correct. Conversely, if the simulated PCIe interface cannot transmit data according to the link bandwidth of x4, it indicates that there is a defect in the design of the integrated circuit. The design code of the PCIe interface can be checked to find and resolve the design defect. In this way, prototype verification of the PCIe interface is achieved.

[0056] In summary, in the technical solutions of some embodiments of the present application, after the PCIe interface is divided into a PCIe controller and a PCIe physical layer, an emulated PCIe controller can be constructed based on the programmable hardware resources in the programmable logic device, and at least part of the physical layer can be selected from the non-programmable hardware resources of the programmable logic device as the emulated PCIe physical layer. After the emulated PCIe controller and the emulated PCIe physical layer are connected, the emulated PCIe controller and the emulated PCIe physical layer can communicate with each other, that is, the combination of the emulated PCIe controller and the emulated PCIe physical layer can be regarded as an emulated PCIe interface. In this way, based on the emulated PCIe interface, prototype verification of the PCIe interface can be achieved, thereby solving the problem that some technologies cannot perform prototype verification on the PCIe interface.

[0057] In some embodiments, the integrated circuit may include multiple PCIe interfaces, and the multiple PCIe interfaces can operate independently of each other. The so-called independent operation means that different PCIe interfaces can operate according to their respective configurations. The configurations of different PCIe interfaces can be the same or different, and the operating states of different PCIe interfaces can have no effect on each other. For example, the data transmission rate of PCIe interfaces t1 and t2 can be 20 Gbps, and the data transmission rate of PCIe interface t3 can be 25 Gbps. For another example, when PCIe interface t1 is configured to be enabled and used for data transmission, PCIe interfaces t2 and t3 can be configured to be disabled and stop being used for data transmission.

[0058] If the integrated circuit includes multiple PCIe interfaces, PCIe prototype verification also includes verifying whether the multiple PCIe interfaces can operate independently according to their respective configurations. For example, when PCIe interface t1 is configured to be enabled and PCIe interfaces t2 and t3 are configured to be disabled, it is necessary to verify whether PCIe interface t1 can transmit data normally during data transmission, and whether PCIe interfaces t2 and t3 have stopped transmitting data.

[0059] In order to achieve prototype verification of multiple PCIe interfaces, in some embodiments, multiple simulated PCIe controllers can be constructed in a programmable logic device, and multiple physical layers can be selected from the physical layer within the programmable logic device and used as simulated PCIe physical layers, thereby obtaining multiple simulated PCIe physical layers. In the case where the programmable logic device includes multiple simulated PCIe controllers and multiple simulated PCIe physical layers, the multiple simulated PCIe controllers can be connected to the multiple simulated PCIe physical layers in a one-to-one correspondence to obtain multiple simulated PCIe interfaces, and different simulated PCIe interfaces are independent of each other. Specifically, multiple simulated high-speed interfaces can be constructed in the programmable logic device, and the simulated PCIe controllers, simulated PCIe physical layers, and simulated high-speed interfaces can be connected in a one-to-one correspondence.

[0060] For example, based on the programmable hardware resources in a programmable logic device, the following simulated PCIe controller and simulated high-speed interface can be constructed:

[0061] Simulated PCIe controller a1, simulated PCIe controller a2, simulated PCIe controller a3;

[0062] Analog high-speed interface c1, analog high-speed interface c2, and analog high-speed interface c3;

[0063] And the following simulated PCIe physical layer can be specified in the physical layer within the programmable logic device:

[0064] Simulate PCIe physical layer b1, simulate PCIe physical layer b2, and simulate PCIe physical layer b3.

[0065] Based on the above-mentioned simulated PCIe controller, simulated PCIe physical layer and simulated high-speed interface, the simulated high-speed interface c1 can be used to connect the simulated PCIe controller a1 and the simulated PCIe physical layer b1 to obtain the simulated PCIe interface t1; the simulated high-speed interface c2 can be used to connect the simulated PCIe controller a2 and the simulated PCIe physical layer b2 to obtain the simulated PCIe interface t2; the simulated high-speed interface c3 can be used to connect the simulated PCIe controller a3 and the simulated PCIe physical layer b3 to obtain the simulated PCIe interface t3.

[0066] The above-mentioned simulated PCIe interface t1, simulated PCIe interface t2 and simulated PCIe interface t3 can be independent of each other, and each simulated PCIe interface has its own corresponding configuration register. In the configuration register, the working mode, rate, etc. of each simulated PCIe interface can be configured separately, and then it is verified whether these simulated PCIe interfaces can operate according to their corresponding configurations. If so, it means that the design logic for multiple PCIe interfaces in the integrated circuit design is correct. If not, it means that there are defects in the design logic for multiple PCIe interfaces in the integrated circuit design, and the design logic of the integrated circuit needs to be checked and modified. In this way, as many potential problems of the integrated circuit as possible can be discovered and solved before the integrated circuit is officially taped out, thereby improving the tape-out success rate of the integrated circuit.

[0067] In the above embodiment, when the integrated circuit includes multiple PCIe interfaces, by constructing multiple simulated PCIe interfaces in the programmable logic device, prototype verification can be performed on the design logic of the multiple PCIe interfaces, thereby improving the coverage of the prototype verification.

[0068] In some embodiments, when the programmable logic device includes multiple analog PCIe interfaces, the method of the present application further includes:

[0069] An analog controller is constructed based on the programmable hardware resources of programmable logic devices. The analog controller includes multiple management ports, which are connected one-to-one with multiple analog PCIe interfaces. The analog controller manages each analog PCIe interface through the management port so that at least some of the analog PCIe interfaces can run simultaneously.

[0070] For easier understanding, please refer to Figure 2 , which is a schematic diagram of the connection between multiple simulated PCIe interfaces and the simulated controller provided in some embodiments of the present application. Figure 2 In the IEEE 802.11 specification, each pair of simulated PCIe controllers and simulated PCIe physical layers connected via PIPE (Platform Interface for Peripheral Equipment) lines constitutes a simulated PCIe interface. The management port of the simulated controller and the simulated PCIe interface are connected via AXI (Advanced eXtensible Interface) lines and APB (Advanced Peripheral Bus) lines.

[0071] Through the APB line (i.e., the management port), the analog controller can configure the operating mode in the analog PCIe interface (i.e., configure the operating mode in the configuration register of the analog PCIe interface). The operating mode may include but is not limited to the rate, link width, etc. of the analog PCIe interface. The operating modes of different analog PCIe interfaces may be different. For example, the rate configured for analog PCIe interface 1 may be 20Gbps, and the rate configured for analog PCIe interface 2 may be 25Gbps. During the prototype verification process, after the analog controller configures each analog PCIe interface, it can detect whether each analog PCIe interface can operate according to its respective configuration. If so, it indicates that the function of the analog PCIe interface is normal; if not, it indicates that the function of the analog PCIe interface is abnormal. In the case of detecting a functional abnormality of the analog PCIe interface, the design code of the PCIe interface can be checked and modified to improve the success rate of the tape-out of the integrated circuit.

[0072] Through the AXI line (i.e., management port), the simulation controller can transmit data with each simulated PCIe interface. Specifically, when prototyping the data transmission function of the PCIe interface, the upper controller (such as the central processing unit, baseboard management controller, etc.) can send data to the simulation controller through the AXI line, and the simulated PCIe controller can send data to the connected simulated PCIe physical layer through the PIPE line. The PCIe physical layer can send the data of the upper controller to other devices through the TX (Transmit) line. If the simulated PCIe interface can send data normally as expected, it means that the function of the simulated PCIe interface is normal, that is, the design code of the PCIe interface is correct. Otherwise, it means that the function of the simulated PCIe interface is abnormal, and the design code of the PCIe interface can be checked and modified.

[0073] Similarly, when prototyping the data receiving function of the PCIe interface, the PCIe physical layer can receive data sent to the upper-level controller by other devices through the RX (Receive) line. After receiving the data, the PCIe physical layer can send the data to the connected simulated PCIe controller through the PIPE line. The simulated PCIe controller can report the data to the simulated controller through the AXI line, and the simulated controller can report the data to the upper-level controller. If the simulated PCIe interface can receive data normally as expected, it means that the function of the simulated PCIe interface is normal, that is, the design code of the PCIe interface is correct. Otherwise, it means that the function of the simulated PCIe interface is abnormal, and the design code of the PCIe interface can be checked and modified.

[0074] Furthermore, in some embodiments, the prototype verification of multiple PCIe interfaces also includes using the multiple PCIe interfaces to send or receive data in parallel, thereby improving the data sending or receiving speed. For example, the data sent by the upper-level controller to other devices can be divided into sub-data groups a1, a2, a3, and a4. Sub-data groups a1 and a2 are then sent through PCIe interface 1, and sub-data groups a3 and a4 are sent through PCIe interface 2. In this way, data can be sent in parallel through multiple PCIe interfaces, greatly improving data efficiency.

[0075] Specifically, when prototyping the function of sending data in parallel by multiple PCIe interfaces, the simulation controller can divide the data sent by the upper-level controller into multiple sub-data groups, and send the multiple sub-data groups to multiple simulated PCIe interfaces through the management port, so that the multiple simulated PCIe interfaces can transmit data in parallel. If the multiple simulated PCIe interfaces can send data in parallel as expected, it means that the function of sending data in parallel by the multiple simulated PCIe interfaces is normal. On the contrary, if the multiple simulated PCIe interfaces cannot send data in parallel as expected, it means that the function of sending data in parallel by the multiple simulated PCIe interfaces is abnormal, and the design code of the PCIe interface can be checked and modified.

[0076] Similarly, when prototyping the function of multiple PCIe interfaces receiving data in parallel, the simulation controller can receive data reported by multiple simulated PCIe interfaces through the management port, aggregate the data reported by the multiple simulated PCIe interfaces, and report the aggregated data to the upper-level controller. If the multiple simulated PCIe interfaces can receive data in parallel as expected, it means that the function of the multiple simulated PCIe interfaces receiving data in parallel is normal. On the contrary, if the multiple simulated PCIe interfaces cannot receive data in parallel as expected, it means that the function of the multiple simulated PCIe interfaces receiving data in parallel is abnormal, and the design code of the PCIe interface can be checked and modified.

[0077] Furthermore, in some embodiments, the prototype verification for multiple PCIe interfaces also includes enabling or disabling control of each PCIe interface separately. For example, PCIe interface 1 and PCIe interface 2 may be enabled while PCIe interface 3 and PCIe interface 4 may be disabled.

[0078] Specifically, when performing prototype verification on the enable or disable control of each PCIe interface, the simulation controller can receive the port configuration information sent by the upper controller, and based on the port configuration information, enable the simulated PCIe interface that needs to be used for data transmission, and disable the simulated PCIe interface that does not need to be used for data transmission. Among them, the enable or disable of each simulated PCIe interface can be controlled in the simulation controller, and there is no need to configure it in the configuration register of the simulated PCIe interface. For example, assuming that it is necessary to enable simulated PCIe interface 1 and simulated PCIe interface 2, and disable simulated PCIe interface 3 and simulated PCIe interface 4, the simulation controller can enable the management port connected to simulated PCIe interface 1 and simulated PCIe interface 2, and disable the management port connected to PCIe interface 3 and PCIe interface 4. If each simulated PCIe interface can be enabled or disabled as expected, it means that the function of the simulated PCIe interface is normal. If each simulated PCIe interface cannot be enabled or disabled as expected, it means that the function of the simulated PCIe interface is abnormal, and the design code of the PCIe interface can be checked and modified.

[0079] In summary, based on the PCIe interface verification method of the present application, prototype verification of the PCIe interface can be achieved, thereby improving the success rate of integrated circuit tape-out.

[0080] Corresponding to the PCIe interface verification method, the present application also provides a PCIe interface verification system located in a programmable logic device. Figure 3 , which is a module diagram of a PCIe interface verification system provided in some embodiments of the present application. Figure 3 In the present invention, the PCIe interface verification system includes a simulated PCIe controller and a simulated PCIe physical layer. The simulated PCIe controller is used to simulate the PCIe controller in the PCIe interface. The PCIe controller is used to perform logical operations related to the PCIe protocol. The simulated PCIe controller is constructed based on the programmable hardware resources in the programmable logic device. The simulated PCIe physical layer is used to simulate the PCIe physical layer in the PCIe interface. The PCIe physical layer is used to transmit PCIe signals. The simulated PCIe physical layer is a non-programmable hardware resource in the programmable logic device. The simulated PCIe controller is connected to the simulated PCIe physical layer to obtain a simulated PCIe interface. The simulated PCIe interface is used for functional verification of the PCIe interface.

[0081] In some embodiments, the PCIe interface verification system includes multiple simulated PCIe controllers and multiple simulated PCIe physical layers. The multiple simulated PCIe controllers are connected to the multiple simulated PCIe physical layers in a one-to-one correspondence to obtain multiple simulated PCIe interfaces. Different simulated PCIe interfaces are independent of each other.

[0082] In some embodiments, the PCIe interface verification system includes an analog controller, which includes multiple management ports, and the multiple management ports are connected one-to-one with multiple simulated PCIe interfaces. The analog controller manages each simulated PCIe interface through the management port so that at least some of the simulated PCIe interfaces can run simultaneously.

[0083] For the working principle of the PCIe interface verification system, please refer to the relevant description of the PCIe interface verification method, which is not repeated here.

[0084] Taking FPGA as an example, in some embodiments, a PCIe interface verification system can be constructed according to the following steps 1) to 4).

[0085] 1) Obtain the first register transfer level (RTL) code for the PCIe interface. This RTL code, also known as the first RTL (Register Transfer Level) code, describes the circuit behavior of the PCIe interface at the register transfer level. This RTL code is the original design code for the PCIe interface. This RTL code can be imported and edited in an HDL (Hardware Description Language) editor. HDL editors include, but are not limited to, Xilinx's Vivado HDL Editor and Altera's Quartus HDL Editor.

[0086] 2) Add the analog controller's second register transfer level code to the first register transfer level code to obtain the target register transfer level code. The second register transfer level code, also known as the second RTL (Register Transfer Level) code, describes the analog controller's circuit behavior at the register transfer level. Adding the second register transfer level code to the first register transfer level code can be performed in an HDL editor.

[0087] 3) When the physical layer in the programmable logic device supports the first communication mode and the PCIe physical layer supports the second communication mode (that is, when the protocol of the physical layer in the programmable logic device does not match that of the PCIe physical layer), the first register transfer level code is changed according to the second communication mode to change the communication mode supported by the PCIe physical layer from the first communication mode to the second communication mode.

[0088] 4) Convert the target register transfer level code into a programmable engineering program compatible with the programmable logic device, and construct the simulated PCIe controller and the simulated controller based on the programmable engineering program. Specifically, the following sub-steps 41) to 45) may be included:

[0089] 41) The target register transfer level code can be imported into a design tool that is compatible with the programmable logic device (such as an FPGA design tool), and an engineering constraint file can be set. In the engineering constraint file, the constraints of the programmable project can be specified. For example, since the programmable logic device includes multiple physical layers, when building a PCIe interface verification system, only one of the physical layers may need to be used. Therefore, the position of the physical layer to be used in the programmable logic device (i.e., the position constraint of the physical layer) can be specified in the engineering constraint file. For another example, when the PCIe interface is not fully compatible with the physical layer in the programmable logic device, it is necessary to specify the clock constraints between the PCIe interface and the physical layer to ensure that the clock signal generated by the physical layer can be applied to the PCIe interface.

[0090] 42) Enter the synthesis process. The synthesis process requires the following operations 421) to 423):

[0091] 421) Perform logical optimization on the RTL code, such as eliminating redundant logic and performing logical reorganization.

[0092] 422) Map the optimized logic to the logic resources provided by the programmable logic device, for example, map the logic operations in the target register transfer level code to basic units such as LUTs (lookup tables), triggers, and multiplexers inside the programmable logic device.

[0093] 423) Generate a gate-level netlist for describing the internal logical connection relationship of the programmable logic device as the basis for subsequent layout and routing.

[0094] 43) Perform layout and routing. Layout and routing requires performing the following operations 431) to 434).

[0095] 431) Allocate logic units (such as LUTs, flip-flops, etc.) in the gate-level netlist to physical locations inside the programmable logic device, i.e. layout.

[0096] 432) Establish physical connections between logic units within a programmable logic device, such as determining the direction, width, and layer allocation of signal lines.

[0097] 433) Map multiple PCIe interfaces into programmable logic devices.

[0098] 434) Generate a configuration file (i.e., a bitstream file) for the PCIe interface. This configuration file includes configuration information and physical connection relationships for all logical units within the simulated PCIe interface. Download this configuration file to the programmable logic device, and configure it based on the configuration file to obtain the simulated PCIe interface.

[0099] 45) Establish a connection between the simulated PCIe interface and other devices outside the programmable logic device.

[0100] At this point, the construction of the PCIe interface verification system can be completed.

[0101] The above is a detailed introduction to a PCIe interface verification method and a PCIe interface verification system provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A PCIe interface verification method, characterized in that: The method comprises: Divide the PCIe interface into a PCIe controller and a PCIe physical layer, wherein the PCIe controller is used to perform logical operations related to the PCIe protocol, and the PCIe physical layer is used to transmit PCIe signals; Building an emulated PCIe controller based on programmable hardware resources in a programmable logic device, and using at least a portion of a physical layer in non-programmable hardware resources of the programmable logic device as an emulated PCIe physical layer; Connecting the simulated PCIe controller and the simulated PCIe physical layer to obtain a simulated PCIe interface; Based on the simulated PCIe interface, functional verification of the PCIe interface is performed.

2. The method according to claim 1, characterized in that The connecting the simulated PCIe controller and the simulated PCIe physical layer to obtain a simulated PCIe interface includes: In the case where the programmable logic device includes multiple simulated PCIe controllers and multiple simulated PCIe physical layers, the multiple simulated PCIe controllers are connected to the multiple simulated PCIe physical layers in a one-to-one correspondence to obtain multiple simulated PCIe interfaces, and different simulated PCIe interfaces are independent of each other.

3. The method according to claim 2, characterized in that In a case where the programmable logic device includes a plurality of simulated PCIe interfaces, the method further includes: Based on the programmable hardware resources of the programmable logic device, an analog controller is constructed, which includes multiple management ports, and the multiple management ports are connected one-to-one with the multiple simulated PCIe interfaces. The analog controller manages each of the simulated PCIe interfaces through the management ports so that at least some of the simulated PCIe interfaces can run simultaneously.

4. The method according to claim 3, characterized in that The simulation controller manages each of the simulated PCIe interfaces through the management port, including: The simulation controller divides the data sent by the upper controller into multiple sub-data groups, and sends the multiple sub-data groups to multiple simulated PCIe interfaces through the management port, so that the multiple simulated PCIe interfaces can transmit data in parallel; And / or, the simulation controller receives data reported by the multiple simulated PCIe interfaces through the management port, aggregates the data reported by the multiple simulated PCIe interfaces, and reports the aggregated data to the upper-level controller.

5. The method according to claim 3, characterized in that The simulation controller manages each of the simulated PCIe interfaces through the management port, including: The simulation controller configures an operating mode in the simulated PCIe interface through the management port, and the simulated PCIe interface operates based on the operating mode configured by the simulation controller.

6. The method according to claim 3, characterized in that The simulation controller manages each of the simulated PCIe interfaces through the management port, including: The simulation controller receives the port configuration information sent by the upper controller, and based on the port configuration information, enables the simulation PCIe interface required for data transmission and disables the simulation PCIe interface not required for data transmission.

7. The method according to claim 3, characterized in that The simulated PCIe controller and the simulated controller are constructed based on the following method: Obtaining a first register transfer level code of the PCIe interface; Adding the second register transfer level code of the analog controller to the first register transfer level code to obtain a target register transfer level code; The target register transfer level code is converted into a programmable project compatible with the programmable logic device, and the simulated PCIe controller and the simulated controller are constructed based on the programmable project.

8. The method according to claim 7, characterized in that After obtaining the first register transfer level code, the method further includes: When the physical layer in the programmable logic device supports a first communication mode and the PCIe physical layer supports a second communication mode, the first register transfer level code is changed according to the second communication mode to change the communication mode supported by the PCIe physical layer from the first communication mode to the second communication mode.

9. A PCIe interface verification system, characterized in that: The system comprises: A simulated PCIe controller, configured to simulate a PCIe controller in a PCIe interface, wherein the PCIe controller is configured to perform logic operations related to the PCIe protocol and is constructed based on programmable hardware resources in a programmable logic device; A simulated PCIe physical layer, used to simulate a PCIe physical layer in the PCIe interface, wherein the PCIe physical layer is used to transmit PCIe signals, and the simulated PCIe physical layer is a non-programmable hardware resource in the programmable logic device; The simulated PCIe controller is connected to the simulated PCIe physical layer to obtain a simulated PCIe interface, and the simulated PCIe interface is used for functional verification of the PCIe interface.

10. The system according to claim 9, characterized in that The system includes multiple simulated PCIe controllers and multiple simulated PCIe physical layers, wherein the multiple simulated PCIe controllers are connected to the multiple simulated PCIe physical layers in a one-to-one correspondence to obtain multiple simulated PCIe interfaces, and different simulated PCIe interfaces are independent of each other; And / or, the system includes an analog controller, the analog controller includes multiple management ports, the multiple management ports are connected one-to-one with the multiple simulated PCIe interfaces, and the analog controller manages each of the simulated PCIe interfaces through the management ports so that at least some of the simulated PCIe interfaces can run simultaneously.

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