Hardware accelerator and chip

Abstract

The embodiment of the invention discloses a hardware accelerator and a chip. The hardware accelerator comprises an interface circuit, and an accelerator core which is coupled to the interface circuit; the interface circuit is used for receiving a first task request and decoding the first task request so as to obtain marking information, as well as configuring the first task request into an FIFO array in match with the marking information according to the marking information; a scheduling controller is used for determining a target channel set with at least one second task request to be treated in the n cycle from at least two channel sets, receiving the time parameters fed back by the accelerator core and respectively corresponding to the targeted channel sets, and scheduling the at least one second task request of the targeted channel sets according to the time parameters and the weighted round robin algorithm; the accelerator core is used for responding to the at least one second task request after scheduling. With the adoption of the hardware accelerator, the isolation in the configuration process can be effectively achieved, so that the mutual influence can be avoided.

Description

technical field [0001] The invention relates to the communication field, in particular to a hardware accelerator and a chip. Background technique [0002] At present, people have developed various types of hardware accelerators to accelerate the execution of certain functions in computer systems, such as graphics accelerators, whose principle is to offload all or part of the graphics functions from the processor to a dedicated hardware accelerator A dedicated hardware accelerator can perform these graphics functions in less time than a processor can. Also includes other types of hardware accelerators like accelerators for processing eXtensible Markup Language, accelerators for performing compression and decompression, floating point processors for performing floating point operations, and accelerators for performing encryption and decryption Accelerators, etc.; in short, any hardware that can perform the functions assigned by the processor can be considered a hardware accel...

AI Technical Summary

Problems solved by technology

However, in different scenarios, in order to ensure that the common-mode accelerator maintains the expected processing capacity for task requests of different communication systems, each processor core needs to communicate with each other to balance the processing of the common-mode accelerator among various communication systems. At this time, if the processor cores responsible for different communication systems access the register space of a common-mode accelerator, it is necessary to ensure that the various communication systems cannot affect each other. Otherwise, once an access error occurs, another communication system will be triggered. The register parameters of the common mode accelerator are modified, that is, the error of one communication system affects the work of another communication system. In addition, the data, messages, interrupts, etc. Resources of another communication system, such as data space, interrupt number, etc., otherwise it will cause errors in another communication system

It can be seen that the communication process between each processor core will be quite complicated and error-prone

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