Delay-locked loop, voltage-controlled delay line and delay unit

Abstract

The embodiment of the invention discloses a delay unit, a voltage-controlled delay line and a delay-locked loop. The delay unit comprises multiple current hunger buffers connected in series. Load capacitors are connected between output of each current hunger buffer and a power voltage and between the output and the ground respectively in series. The voltage-controlled delay line is formed by cascading one or more delay units. The delay-locked loop comprises an offset generation circuit and the voltage-controlled delay line, the offset generation circuit outputs voltage control signals Vbp and Vbn controlling the voltage-controlled delay line, and the voltage-controlled delay line comprises an internal voltage-controlled delay line for phase locking and one or more parallel external voltage-controlled delay lines providing delay clocks, wherein the internal voltage-controlled delay line and the external voltage-controlled delay lines each comprise one or more cascaded delay units. The delay unit, the voltage-controlled delay line and the delay-locked loop are suitable for high-speed circuits, connecting lines on the high-speed clocks can be reduced through the delay-locked loop, and the problem that clock accuracy is insufficient due to the fact that the connecting lines are long is solved.

Description

technical field [0001] The invention relates to the communication field, in particular to a delay-locked loop, a voltage-controlled delay line and a delay unit. Background technique [0002] In data transmission, as the amount of data transmission increases, the clock frequency becomes higher and higher, and the requirements for synchronous clocks become more and more stringent. In order to increase the data transmission rate, the easy way is to use the rising and falling edges of the clock to collect data at the same time, so as to double the efficiency at the same rate. In addition, during data processing, clocks with different phases are also required, for example: 45° phase clocks or 90° phase clocks, etc., and these clocks are required to maintain a good duty cycle. Currently, the generation of these phase clocks can be implemented by a DLL (Delay Locked Loop, delay locked loop). [0003] figure 1 shows the structure of a typical DLL. [0004] like figure 1 As show...

AI Technical Summary

Problems solved by technology

[0007] this kind figure 2 The delay unit of the structure can only be used when the clock is relatively slow, and when the clock frequency reaches hundreds of MHZ or even GHz, it will be powerless

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