Self-alignment channel doping for restraining CMOS (Complementary Metal Oxide Semiconductor) short channel effect and preparation method thereof

Abstract

The invention relates to self-alignment channel doping for restraining a CMOS (Complementary Metal Oxide Semiconductor) short channel effect and a preparation method thereof, which solve the following problems in the prior art: 1, doping of a source and a drain is compensated to cause the increase of parasitic resistances of the source and the drain; 2, profiles of PN junctions of a source substrate and a drain substrate are influenced to cause the increase of reversed biased leakage current of the source substrate and the drain substrate; and 3, the junction depth Xj of the PN junctions of the source substrate and the drain substrate can be increased to cause counteractive on the restraint on the SCE (Short Channel Effect). According to the self-alignment channel doping for restraining the CMOS short channel effect and the preparation method thereof, disclosed by the invention, self-alignment doping on CMOS device channel regions is realized, a heavy-doped buried layer under a channel is formed, and source and drain regions are not influenced, thus the SCE is effectively restrained, and the performances of devices are improved.

Description

Technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a self-aligned channel doping suppressing CMOS short channel effect and a preparation method thereof. Background technique [0002] The short channel effect (Short Channel Effect) is a common phenomenon when the channel length of CMOS devices is reduced. It will cause threshold voltage drift, source-drain punch-through, DIBL (Drain induction barrier lower, lower drain induction barrier) (higher drain Depression) and other characteristics will cause the performance of CMOS devices to fail in severe cases. SCE can be explained by the charge sharing model proposed by Yau: [0003] [0004] That is, when the channel becomes shorter, the ratio of the source-line and drain-line PN junction sharing the channel depletion region charge to the channel total charge will increase, resulting in a decrease in gate control capability. [0005] According to the threshold voltage drift formul...

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Problems solved by technology

[0007] The invention discloses a self-aligned channel doping to suppress the CMOS short channel effect and a preparation method thereof, which are used to solve the problems in the prior art: 1. The source-drain doping will be compensated, resulting in an increase in the parasitic resistance of the source-drain ; 2. It will affect the profile of the source lining and drain lining PN junction, causing their reverse bias leakage current to increase; 3. It may increase the junction depth Xj of the source lining and drain lining PN junction, which will have a negative effect on suppressing SCE question

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