Sub-threshold digital circuit time sequence optimization method and system

Abstract

The invention discloses a sub-threshold digital circuit time sequence optimization method and system. The method comprises the following steps: firstly, determining a logic unit circuit capable of improving the performance by utilizing a reverse short channel effect; performing time sequence analysis on a given integrated circuit to obtain all signal paths which do not meet the time sequence requirement; then determining a plurality of main delay units capable of improving the performance by utilizing a reverse short channel effect in each signal path which does not meet the time sequence requirement; and finally, increasing the gate length of the device of the main time delay unit by using a reverse short channel effect according to a preset time sequence constraint condition to carry outadjustment, and adjusting the gate length size to optimize the time sequence of the sub-threshold digital circuit. According to the invention, the gate length of a device of a main time delay unit isincreased by using a reverse short channel effect, so that time sequence optimization is realized, the circuit performance of a sub-threshold digital circuit is improved, and the time delay time of the unit is reduced; and meanwhile, the consistency of unit delay is improved by increasing the area, so that the robustness of the circuit is enhanced.

Description

technical field [0001] The invention relates to the technical field of circuit timing optimization, in particular to a sub-threshold digital circuit timing optimization method and system. Background technique [0002] Subthreshold digital circuits refer to digital logic circuits whose operating voltage is lower than the threshold voltage of transistor devices. Since the circuit operates in the subthreshold region, the dynamic power consumption and static power consumption of the circuit can be greatly reduced. It is precisely because the device works in the sub-threshold region that the current and voltage of the device have an exponential relationship, and changes in the size of the device will lead to significant changes in current and parasitic capacitance, thereby significantly changing the electrical performance of the circuit. In addition, circuit performance fluctuates greatly with PVT (Process-Voltage-Temperature, process-temperature-voltage) deviation. In order to m...

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Problems solved by technology

It is precisely because the device works in the sub-threshold region that the current and voltage of the device have an exponential relationship, and the change in the size of the device will lead to obvious changes in current and parasitic capacitance, which will significantly change the electrical performance of the circuit.

In addition, circuit performance fluctuates greatly with PVT (Process-Voltage-Temperature, process-temperature-voltage) deviation. In order to make the designed sub-threshold digital circuit have high robustness, the design optimization process of sub-threshold digital circuit Statistical analysis and optimization of PVT deviation need to be considered in the process, which will exponentially increase the complexity of device size optimization for sub-threshold digital circuits, making the process of device optimization speed extremely slow

[0003] At present, with the increase in the scale of sub-threshold digital circuits, the combination of statistical analysis and optimization of PVT deviations with traditional stochastic optimization algorithms and heuristic optimization algorithms has been unable to be directly applied to large-scale sub-threshold digital circuits. Optimization, especially the optimization that cannot be directly applied to large-scale sub-threshold digital sequential circuits

In addition, in order to improve the performance of sub-threshold digital circuits, the traditional method is to increase the gate width / gate length ratio of MOS devices in the circuit. However, increasing the gate width will significantly increase the area, which will cause the cell height in the standard cell library used discretization, further resulting in waste of area; while reducing the gate length of the unit working in the subthreshold region, it may reduce the performance of the unit due to the reverse short channel effect, and at the same time due to the reduction of the product of gate width-gate length. Leads to a flatter performance distribution of the unit, reducing the robustness of the circuit design

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