Sub-threshold digital circuit time sequence optimization method and system

A digital circuit, sub-threshold technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of reducing unit performance, slow device optimization speed, increasing area, etc., to improve circuit performance and realize timing Optimize and reduce the effect of delay time
CN110956008APending Publication Date: 2020-04-03INST OF MICROELECTRONICS CHINESE ACAD OF SCI
0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN Β· China
Current Assignee / Owner
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Publication Date
2020-04-03

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

The invention discloses a sub-threshold digital circuit time sequence optimization method and system. The method comprises the following steps: firstly, determining a logic unit circuit capable of improving the performance by utilizing a reverse short channel effect; performing time sequence analysis on a given integrated circuit to obtain all signal paths which do not meet the time sequence requirement; then determining a plurality of main delay units capable of improving the performance by utilizing a reverse short channel effect in each signal path which does not meet the time sequence requirement; and finally, increasing the gate length of the device of the main time delay unit by using a reverse short channel effect according to a preset time sequence constraint condition to carry outadjustment, and adjusting the gate length size to optimize the time sequence of the sub-threshold digital circuit. According to the invention, the gate length of a device of a main time delay unit isincreased by using a reverse short channel effect, so that time sequence optimization is realized, the circuit performance of a sub-threshold digital circuit is improved, and the time delay time of the unit is reduced; and meanwhile, the consistency of unit delay is improved by increasing the area, so that the robustness of the circuit is enhanced.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention relates to the technical field of circuit timing optimization, in particular to a sub-threshold digital circuit timing optimization method and system. Background technique

[0002] Subthreshold digital circuits refer to digital logic circuits whose operating voltage is lower than the threshold voltage of transistor devices. Since the circuit operates in the subthreshold region, the dynamic power consumption and static power consumption of the circuit can be greatly reduced. It is precisely because the device works in the sub-threshold region that the current and voltage of the device have an exponential relationship, and changes in the size of the device will lead to significant changes in current and parasitic capacitance, thereby significantly changing the electrical performance of the circuit. In addition, circuit performance fluctuates greatly with PVT (Process-Voltage-Temperature, process-temperature-voltage) deviation. In order to m...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More