50 results about "Indium gallium nitride" patented technology

The invention relates to the technical field of semiconductor devices, in particular to an epitaxial structure of an LED quantum well and a growth method of the epitaxial structure. Comprising an active layer, the active layer is formed by periodically stacking a plurality of unit structures, each unit structure comprises a quantum well layer, a cover layer and a quantum barrier layer which grow in sequence, and the quantum well layer comprises a superlattice structure formed by an indium gallium nitride layer and a processing layer which grow alternately. The growth time of indium gallium nitrogen is short, the thickness of a single layer is 5%-15% of the thickness of traditional indium gallium nitrogen, the pressure stress borne by indium gallium nitrogen is greatly reduced, and the crystal quality of the quantum well is improved. Moreover, after the indium gallium nitrogen grows for a short time, the ammonia gas and indium are kept for treatment, so that the nitrogen vacancy defect can be reduced, the decomposition of indium in the indium gallium nitrogen can be reduced, and the defects in a quantum well are reduced. According to the invention, the crystal quality of the quantum well is obviously improved, and the luminous efficiency of an LED under low current density is obviously improved.

A beam laser diode takes a silicon-based nitride epitaxial wafer as a carrier and comprises a silicon substrate layer, an aluminum nitride layer, a u-type gallium nitride layer, an n-type gallium nitride layer, a quantum well layer, a p-type gallium nitride layer and a SiO2 layer which are sequentially arranged from bottom to top, the p-type electrode is arranged on the p-type gallium nitride layer, and the n-type electrode is arranged on the edge of the n-type gallium nitride layer. A nitride material on a silicon substrate is used for preparing a micro-beam stress sensitive area LD by utilizing photoetching and ICP (Inductively Coupled Plasma) etching processes for emitting light, and after electrification, the laser LD is obtained in the stress sensitive area of the beam. Under the power-on condition, before and after acceleration loading, due to the fact that quantum limits the stark effect, the frequency wavelength of laser changes, and the magnitude of the acceleration can be sensed through difference frequency.

Embodiments of the present description provide a semiconductor green laser. The semiconductor green laser successively comprises, from bottom to top, a substrate (100), a lower confinement layer (101), a lower waveguide layer (102), an active layer (103), an upper waveguide layer (104), and an upper confinement layer (105). The active layer (103) is a quantum well consisting of a well layer and a barrier layer, the period of the quantum well is z, and z is greater than or equal to 1 and less than or equal to 3; the well layer comprises any one or any combination of aluminum indium gallium nitride (AlInGaN), aluminum indium nitrogen (AlInN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), indium nitride (InN), indium gallium nitrogen (InGaN), and gallium nitride (GaN), the thickness of the well layer is p, and p is greater than or equal to 5 angstroms and less than or equal to 100 angstroms; the barrier layer comprises any one or any combination of AlInGaN, AlInN, AlGaN, AlN, InN, InGaN, and GaN, the thickness of the barrier layer is q, and q is greater than or equal to 10 angstroms and less than or equal to 200 angstroms; and the electron effective mass of the well layer is smaller than that of the barrier layer, the spontaneous polarization coefficient of the well layer is smaller than that of the barrier layer, and the band gap of the well layer is smaller than that of the barrier layer.

A method for achieving voltage-controlled gate-modulated light emission using monolithic integration of fin- and nanowire- n-i-n vertical FETs with bottom-tunnel junction planar InGaN LEDs is described. This method takes advantage of the improved performance of bottom-tunnel junction LEDs over their top-tunnel junction counterparts, while allowing for strong gate control on a low-cross-sectional area fin or wire without sacrificing LED active area as in lateral integration designs. Electrical modulation of 5 orders, and an order of magnitude of optical modulation are achieved in the device.

Disclosed is a system and method for solid-state 2D optical phased arrays (OPAs), which are fabricated from InGaN / AlGaN multiple quantum wells (MQWs) and AlyGa1-yN / AlxGa1-xN (y<x) MQWs. The InGaN / AlGaN MQWs and AlyGa1-yN / AlxGa1-xN (y<x) MQWs include alternating p-type and n-type layers to form p-n-p-n MQW structures to allow the OPA to operate in the reversed biased configuration to further minimize the operating current and heat generation. The phase in each pixel within the OPA will be controlled independently via electro-optic effect in III-nitride MQWs by varying the voltage in each pixel by a Si CMOS array to achieve the manipulation of the distribution of optical power in the far field and steering of the main laser beam. The present disclosure is applicable to a wide range of applications, including the operation of LIDAR systems, laser weapons, laser illuminators, and laser imaging systems.

Exemplary processing methods of forming a semiconductor structure may include forming subpixels on a substrate. Each of the subpixels may include a gallium-and-nitrogen-containing layer formed on an exposed portion of a nucleation layer on the substrate. The subpixels may further include a porosified region formed on or in the gallium-and-nitrogen-containing region, and an active region formed on the porosified region. The active region may include an indium-gallium-and-nitrogen-containing material. The processing methods may further include forming a first reflection layer around one of the subpixels, wherein the first reflection layer includes a first metal layer. The methods may additionally include forming a second reflection layer around another of the subpixels, wherein the second reflection layer includes a second metal that is different than the first metal.

A method for manufacturing a semiconductor optical electrode, said method including: a step for forming n-type gallium nitride 12 on a substrate 11; a step for forming indium gallium nitride 13 on the n-type gallium nitride 12; and a step for forming p-type nickel oxide 14 on the indium gallium nitride 13. In the step for forming the p-type nickel oxide, nickel oxide is sputtered in an atmosphere in which oxygen is mixed with a sputtering gas.

The present disclosure discloses a light-emitting diode epitaxial wafer for improving reliability and a preparation method thereof, belonging to the field of light-emitting diode fabrication. The p-type composite contact layer on the p-type GaN layer includes a first aluminum gallium nitride sublayer, a second aluminum gallium nitride sublayer, a third aluminum indium gallium nitride sublayer, a fourth aluminum indium gallium nitride sublayer, and a fifth indium gallium nitride sublayer that are sequentially stacked. The p-type composite contact layer with a relatively large thickness and several potential barrier changes avoids the occurrence of current breakdown. It can also make the carriers more evenly distributed in the P electrode region, effectively reduce the poor antistatic ability caused by uneven carrier distribution, and improve the reliability of the light-emitting diode light-emitting device. The doping concentrations of Mg in the first aluminum gallium nitride sublayer, the second aluminum gallium nitride sublayer, the third aluminum indium gallium nitride sublayer, the fourth aluminum indium gallium nitride sublayer, and the fifth indium gallium nitride sublayer increase in sequence, which may reduce the resistance, lower the working voltage, and reduce the probability of current breakdown, thereby improving the reliability of the light-emitting diode.

The present disclosure provides a method for preparing a semiconductor quantum well structure, comprising: forming an n-type semiconductor layer on one side of a substrate; forming a multi-quantum well structure on the side of the n-type semiconductor layer facing away from the substrate, the multi-quantum well structure comprising quantum barrier layers and quantum well layers that are alternately arranged, the material of the quantum well layer comprising: indium gallium nitride, the quantum barrier layer comprising: a barrier layer base layer and a barrier layer modulation layer located on the side of the barrier layer base layer facing away from the substrate, the barrier layer modulation layer comprising a plurality of first raised stripes that are periodically arranged along a preset first direction, the quantum well layer comprising: a well layer base layer and a well layer modulation layer located on the side of the well layer base layer facing away from the substrate, the well layer modulation layer comprising a plurality of second raised stripes that are periodically arranged along a preset second direction, one of the preset first direction and the preset second direction being a circumferential direction of the substrate, and the other being a radial direction of the substrate; forming a p-type semiconductor layer on the side of the multi-quantum well structure facing away from the substrate.

The proposed solution relates to a semiconductor device (30) comprising an epiwafer (10) and wherein a plurality of InGaN platelets (100), each InGaN platelet being monolithically grown on the epiwafer and configured with a top c-plane surface. An upper mask layer (200) is provided with mask apertures (220) over the InGaN platelets, wherein said mask apertures have a width which is smaller than said top c-plane surface. A plurality of microLED structures (240) comprising quantum well, QW, layers (242), are grown on the top c-plane surface in one of said mask apertures. The solution further relates to a microLED device (500) comprising the semiconductor device, and a method for fabricating the semiconductor device.

Provided is a method for producing a nitride semiconductor photoelectrode capable of improving the light energy conversion efficiency. The method for producing a nitride semiconductor photoelectrode includes a first step of forming an n-type gallium nitride layer on an insulating or conductive substrate, a second step of forming an indium gallium nitride layer on the n-type gallium nitride layer, a third step of forming a nickel layer n the indium gallium nitride layer, and a fourth step of heat-treating the nickel layer in an oxygen atmosphere.

The application provides a monolithic integrated micron LED chip, comprising a substrate and a plurality of micron LED devices, the micron LED device comprising an n-gallium nitride layer, an indium gallium nitride / gallium nitride multiple quantum well structure, a p-aluminum gallium nitride layer, a p-gallium nitride layer, a current diffusion layer and a passivation layer, the quantum barrier thickness is 0.5-5 nm, the monolithic integrated micron LED chip can be used for light detection through a high-voltage bias circuit, the high-voltage bias circuit provides a reverse bias voltage of 0-200 V and a bandwidth of 10 MHz-10 GHz; the monolithic integrated micron LED chip can be used for light emission and has a bandwidth of 10 MHz-10 GHz. The monolithic integrated micron LED chip has good photoelectric response characteristics and bandwidth characteristics under an extremely high reverse bias voltage. The application also provides an application of the monolithic integrated micron LED chip as a narrowband photoelectric detector and an application in high-speed visible light communication, and a visible light communication device.

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source / drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source / drain contact disposed on the source / drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

Exemplary processing methods of forming a semiconductor structure may include forming subpixels on a substrate. Each of the subpixels may include a gallium-and-nitrogen-containing layer formed on an exposed portion of a nucleation layer on the substrate. The subpixels may further include a porosified region formed on or in the gallium-and-nitrogen-containing region, and an active region formed on the porosified region. The active region may include an indium-gallium-and-nitrogen-containing material. The processing methods may further include forming a first reflection layer around one of the subpixels, wherein the first reflection layer includes a first metal layer. The methods may additionally include forming a second reflection layer around another of the subpixels, wherein the second reflection layer includes a second metal that is different than the first metal.

A method of manufacturing a substrate, comprising the steps of: providing a stack comprising an initial substrate, a gallium nitride layer, a doped indium gallium nitride layer (13), and an unintentionally doped indium gallium nitride layer (14); transferring the doped indium gallium nitride layer (13) and the unintentionally doped indium gallium nitride layer (14) to an anodization support (21) to form a second stack (20); immersing the second stack (20) and a counter electrode in an electrolyte solution and applying a voltage or a current between the doped indium gallium nitride layer (13) and the counter electrode to porous the doped indium gallium nitride layer (13) and to relax the unintentionally doped indium gallium nitride layer (14); transferring the doped indium gallium nitride layer (13) and the unintentionally doped indium gallium nitride layer (14) to a support of interest; and forming an indium gallium nitride layer by epitaxy on the unintentionally doped indium gallium nitride layer to obtain a relaxed epitaxially grown indium gallium nitride layer.

A method for forming an indium gallium nitride quantum well structure is disclosed. The method includes forming a gallium nitride microdisk on a substrate, with the gallium nitride microdisk having an inverted pyramid form and an end face; and forming multiple quantum well layers on the end face, with each quantum well layer including an indium gallium nitride quantum well and a barrier layer. The indium gallium nitride quantum well is grown at a growth temperature adjusted using a trend equation within a temperature range of 480° C. to 810° C.

To obtain a high-quality semiconductor laminate and a high-quality semiconductor element. [Solution] Provided is a semiconductor laminate including a substrate that includes silicon carbide and has a main surface, a first layer that is provided on the main surface of the substrate and includes an aluminum nitride crystal, a second layer that is provided on the first layer and includes a crystal of any of aluminum gallium nitride, aluminum indium nitride, and aluminum indium gallium nitride, and a third layer that is provided on the second layer and includes a gallium nitride crystal, in which the first layer has tensile strain in a direction along the main surface at 27° C.

The invention provides a monolithic integrated micron-sized LED chip, which comprises a substrate and a plurality of micron-sized LED devices, each micron-sized LED device comprises an n-gallium nitride layer, an indium gallium nitride / gallium nitride multi-quantum well structure, a p-aluminum gallium nitride layer, a p-gallium nitride layer, a current diffusion layer and a passivation layer, the thickness of a quantum barrier is 0.5-5nm, and the thickness of the current diffusion layer is 0.5-5nm. The monolithic integrated micron-sized LED chip can be used for optical detection through the high-voltage bias circuit, the high-voltage bias circuit provides a reverse bias voltage of 0-200V, and the bandwidth of the high-voltage bias circuit is 10MHz-10GHz; the monolithic integrated micron-sized LED chip can be used for light emission, and the bandwidth of the monolithic integrated micron-sized LED chip is 10 MHz to 10 GHz. The monolithic integrated micron-sized LED chip disclosed by the invention has better photoelectric response characteristic and bandwidth characteristic under extremely high reverse bias voltage. The invention further provides application of the monolithic integrated micron-sized LED chip as a narrow-band photoelectric detector and application of the monolithic integrated micron-sized LED chip in high-speed visible light communication, and further provides a visible light communication device.

The application discloses an indium gallium nitride quantum well optomechanical microcavity accelerometer with quantum limited stark effect, and a beam laser diode takes a silicon-based nitride epitaxial wafer as a carrier and comprises a silicon substrate layer, an aluminum nitride buffer layer, an n-type gallium nitride layer, a quantum well layer, a p-type gallium nitride layer and a SiO2 layer which are sequentially arranged from bottom to top, a p-type electrode arranged on the p-type gallium nitride layer and an n-type electrode arranged at the edge of the n-type gallium nitride layer. The nitride material on the silicon substrate is prepared by using a photoetching and ICP etching process to realize LD light emission of a micro-beam stress sensitive area. After power-on, laser LD is obtained at the stress sensitive area of the beam. Under the power-on condition, the frequency wavelength of the laser changes before and after acceleration load due to the quantum limited stark effect, and the acceleration size can be perceived through the difference frequency.

The invention discloses an epitaxial structure for improving luminous efficiency and a preparation method of the epitaxial structure. The epitaxial structure comprises a substrate, an N-type semiconductor layer, a first current expansion layer, an active layer, a second current expansion layer and a P-type semiconductor layer which are sequentially stacked from bottom to top, the first current expansion layer is an InGaN (indium gallium nitride)-GaN (gallium nitride)-AlGaN (gallium nitride) composite layer, and two-dimensional electron gas is generated on a heterogeneous interface by the InGaN / GaN and the GaN / AlGaN; the second current expansion layer is an InGaN-GaN-AlGaN composite layer with an In component and an Al component gradually changed, and through the arrangement of a double-layer InGaN-GaN-AlGaN current expansion layer structure, electron leakage is reduced, hole injection is increased, carrier transportation is balanced, and the luminous efficiency of the device is improved.

The present invention provides an indium gallium nitride (InGaN) layer having a substantially relaxed region, and a device fabricated on the InGaN layer. [Solution] An InGaN layer is disclosed, characterized in that its in-plane lattice constant is in the range of 3.19 Å to 3.50 Å. The InGaN layer is grown by accreting InGaN grown on multiple GaN seed regions. This InGaN layer can be used to fabricate optical and electronic devices for use as light sources in lighting and display applications.

A light emitting device including an N-polar semiconductor nanowire region having a first doping type. An indium gallium nitride / gallium nitride (InGaN / GaN) N-polar short period superlattice (SPSL) region of each nanowire, having a fist doping type, can be disposed on the N-polar semiconductor region. An indium gallium nitride (InGaN) N-polar single-segment (SS) active region of each nanowire can be disposed on the InGaN / GaN N-polar short period superlattice (SPSL) region opposite the N-polar semiconductor region. A tunnel junction region of each nanowire, having a second doping type, can be disposed on the InGaN N-polar single-segment (SS) active region opposite the InGaN / GaN N-polar short period superlattice (SPSL) region.

The application discloses a flexible brain-computer interface composite device and a preparation method thereof. The flexible brain-computer interface composite device comprises a flexible substrate, a bottom electrode layer, a functional film layer and a top electrode layer which are arranged in a stack; the functional film layer comprises a first epitaxial layer, a light-emitting layer and a second epitaxial layer which are arranged in a stack from the bottom electrode layer to the top electrode layer; one of the first epitaxial layer and the second epitaxial layer is an n-type doped semiconductor material, and the other is a p-type doped semiconductor material; and the material of the light-emitting layer is indium gallium nitride. The application can combine the functions of collecting brain electrical signals, emitting light stimulation signals and providing energy for the device into the same device structure, so that the volume of the brain-computer interface device can be reduced and the integration degree can be improved.

The invention provides a high-quality semiconductor laminate, a semiconductor element, and a method for manufacturing the semiconductor laminate. This semiconductor laminate is provided with: a substrate that contains silicon carbide and has a main surface; a first layer that is provided on the main surface of the substrate and contains crystals of aluminum nitride; the second layer is arranged on the first layer and comprises any crystal of aluminum gallium nitride, aluminum indium nitride or aluminum indium gallium nitride; and a third layer that is provided on the second layer and contains a crystal of gallium nitride, the first layer having a tensile strain at 27 DEG C in a direction along the main surface.

A method of forming an LED emitter includes: providing a III-nitride layer on a substrate (310), the III-nitride layer having a planar top surface; providing discrete lateral growth regions on the top surface; selectively epitaxially growing, on each discrete lateral growth region, a base region (1210) comprising an In(x)Ga(1-x)N material, each extending perpendicular to the top surface; providing surfaces of the In(x)Ga(1-x)N material on portions of the base regions (1210), the surfaces having a relaxed strain and being characterized by a base lattice constant within 0.1% of its bulk relaxed value; and epitaxially growing LED regions on the surfaces, the LED regions including light-emitting layers of In(y)Ga(1-y)N material that are pseudomorphic with the surfaces of the In(x)Ga(1-x)N material, and characterized by an active region (1240) lattice constant within 0.1% of the base lattice constant, wherein 0.05<x<0.2 and y>0.3.

An epitaxial structure including at least a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a P-type aluminum indium gallium nitride layer is provided. The nucleation layer is formed on the substrate; the buffer layer is formed on the nucleation layer; the channel layer is formed on the buffer layer; the barrier layer is formed on the channel layer; and the P-type aluminum indium gallium nitride layer is formed on the barrier layer. The material of the P-type aluminum indium gallium nitride layer is AlInGaN with a P-type dopant, in which the contents of Al, In and Ga all change stepped-periodically or stepped-periodical-gradually in the thickness direction, and the doping concentration of the P-type dopant changes stepped-periodically or stepped-periodical-gradually in the thickness direction.

A vertical-cavity surface-emitting laser (VCSEL) includes a first reflector structure; a second reflector structure; and an active region arranged between the first reflector structure and the second reflector structure. The active region comprises a multi-quantum-well (MQW) structure; a spacer arranged above the MQW structure; an electron blocking layer arranged above the spacer layer; and a p-type structure doped with p-type dopants, the p-type structure arranged above the electron blocking layer and between the first reflector structure and the electron blocking layer. The spacer and / or the p-type structure comprises Indium Gallium Nitride (InGaN).