14 results about "Indium nitride" patented technology

The present invention relates to the field of semiconductors, and in particular to a method for preparing a TMBS device, comprising the following steps: step 1, using a single crystal silicon material as a substrate material; step 2, forming an indium nitride buffer layer on the upper surface of the substrate base by chemical vapor deposition; step 3, growing a layer of indium germanium antimonide as an epitaxial layer on the surface of the buffer layer by chemical vapor deposition; step 4, opening a groove; step 5, setting a Schottky barrier and a metal layer, and obtaining the desired TMBS device. The epitaxial layer used in the present invention is indium germanium antimonide, which has lower surface defects and better breakdown resistance than indium antimonide, so that the TMBS device has a wide range of application prospects in the fields of power electronics, new energy vehicles, and photovoltaics.

An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

The present invention provides a semiconductor structure comprising: a silicon substrate in [100] orientation; a scandium oxide layer over the substrate, in [111] orientation; and a scandium-rare earth-oxide layer over the scandium oxide layer. The scandium-rare earth-oxide layer can have a graded composition to transition lattice constant to match to a subsequent layer, such as an indium nitride layer having very high electron drift velocity. InN over Si (100) offers transistors, photonics and passive electronics that operate in the terahertz frequency range.

The present disclosure relates to an integrated chip structure. The integrated chip structure includes a plurality of conductive layers disposed over a substrate and a plurality of dielectric layers disposed over the substrate and alternately interleaved with the plurality of conductive layers. A channel layer extends along sides of the plurality of conductive layers and the plurality of dielectric layers. A ferroelectric layer is disposed between the channel layer and the plurality of conductive layers. The ferroelectric layer includes wurtzite-based aluminum nitride, indium nitride, or gallium nitride and further includes scandium nitride or yttrium nitride.

To provide a gallium nitride (GaN) high electron mobility transistor with improved component current and output power.SOLUTION: The high electron mobility transistor 100 includes a substrate 1, a barrier layer 2, a semiconductor layer 3, an insertion layer 4, a passivation layer 5, a drain electrode 61, a source electrode 62, and a gate electrode 63. The barrier layer 2 is disposed on the substrate 1 and includes aluminum gallium indium nitride. The semiconductor layer 3 is disposed between the substrate 1 and the barrier layer 2. The insertion layer 4 is disposed between the semiconductor layer 3 and the barrier layer 2 and contains aluminum gallium nitride. The thickness of the barrier layer may range from 3nm to 40nm. The passivation layer 5 is arranged on the barrier layer 2 and comprises silicon nitride. The drain electrode 61 and the source electrode 62 are disposed on the barrier layer 2, and the gate electrode 63 is disposed on the passivation layer 5.SELECTED DRAWING: Figure 1

The semiconductor structure (1) comprises a substrate (100) and an epitaxial III-N semiconductor layer stack (200) overlying the substrate (100). The epitaxial III-N semiconductor layer stack (200) comprises a first active III-N layer (201), a spacer layer (202) overlying the first active III-N layer (201), a diffusion barrier layer (203) overlying the spacer layer (202), and a second active III-N layer (204) overlying the diffusion barrier layer (203) and comprising indium aluminum nitride. A two-dimensional electron gas (20) is located between the first active III-N layer (201) and the second active III-N layer (204). The diffusion barrier layer (203) comprises gallium nitride, and the thickness of the diffusion barrier layer (203) is less than 1 nm.

Freestanding substrate (21] for epitaxial crystal growth, wherein the freestanding substrate (21] comprises a crystal of a Group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride, or a solid solution thereof; wherein the freestanding substrate (21) comprises a nitrogen polar surface (21a) and a group 13 element polar surface (21b); wherein the nitrogen polar surface (21a) is curved into a convex shape; wherein the nitrogen polar surface (21a) comprises an outer peripheral part (22) with a chamfer part (21c); and wherein an absolute value of a radius of curvature of the fault of the element-of-group 13 polar surface (21b) is smaller than an absolute value of a radius of curvature of the fault of the nitrogen polar surface (21a).

A semiconductor device includes: a channel layer; a barrier layer that is provided above the channel layer and includes indium aluminum gallium nitride (InAlGaN); a first insulating layer provided on the barrier layer; and a second insulating layer provided on the first insulating layer, wherein the first insulating layer is a silicon nitride layer that includes one or more types of group III elements included in the barrier layer.

On the basis of a self-supporting substrate for epitaxial crystal growth containing a Group 13 element nitride crystal selected from gallium nitride, aluminum nitride, indium nitride, or a mixed crystal thereof, cracking of the self-supporting substrate or the epitaxial crystal in a process of growing the epitaxial crystal is prevented. A self-supporting substrate for epitaxial crystal growth (21) containing a Group 13 element nitride crystal selected from gallium nitride, aluminum nitride, indium nitride, or a mixed crystal thereof has a nitrogen-polarity face (21a) and a Group 13 element-polarity face (21b). The nitrogen-polarity face (21a) is convexly curved, and a chamfered portion (21c) is provided at an outer peripheral portion (22) of the nitrogen-polarity face (21a).

A high electron mobility transistor includes a substrate, a barrier layer, a semiconductor layer and an insertion layer. The barrier layer is disposed on the substrate and includes aluminum gallium indium nitride. The semiconductor layer is disposed between the substrate and the barrier layer. The insertion layer is disposed between the semiconductor layer and the barrier layer, and includes aluminum gallium nitride.

A group 13 nitride crystal layer is composed of a group 13 nitride crystal selected from gallium nitride, aluminum nitride, indium nitride or the mixed crystals thereof, and the group 13 nitride crystal layer includes an upper surface and bottom surface. The group 13 nitride crystal layer includes high-luminance layers and low-luminance layers being present alternately, and the low-luminance layers have thicknesses of 3 or larger and 10 or smaller provided that 1 is assigned to a thickness of the high-luminance layer, when a cross section of the group 13 nitride crystal layer cut in a direction perpendicular to the upper surface is observed by cathode luminescence.

A bandgap tuneable p-GaN high electron mobility transistor (HEMT) having a structure stacked on a silicon carbide substrate. The device incorporates an indium nitride nucleation layer, followed by an aluminum nitride nucleation layer, and a first aluminum gallium nitride buffer layer. A gallium nitride channel layer is deposited on this stack, with an aluminum source and a drain contact at either end. The bandgap tuneable p-GaN HEMT includes a two-dimensional molybdenum disulfide layer over the channel, covered by a second AlGaN buffer layer. A p-type gallium nitride cap layer and a platinum gate contact complete the structure. This configuration facilitates bandgap tuning and strain engineering, enhancing electron mobility and density in the two-dimensional electron gas region, making it suitable for high-power and high-frequency applications.

A free-standing substrate, for growing epitaxial crystal composed of a group 13 nitride crystal selected from gallium nitride, aluminum nitride, indium nitride or a mixed crystal thereof, includes a nitrogen polar surface and group 13 element polar surface. The nitrogen polar surface is warped in a convex shape, and a chamfer part is provided in an outer peripheral part of the nitrogen polar surface.

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source / drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source / drain contact disposed on the source / drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.