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76results about How to "Improve charge balance" patented technology

Power semiconductor devices and methods of manufacture

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.
Owner:SEMICON COMPONENTS IND LLC

Power semiconductor devices and methods of manufacture

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.
Owner:SEMICON COMPONENTS IND LLC

Power semiconductor devices and methods of manufacture

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.
Owner:SEMICON COMPONENTS IND LLC

Apparatus and method for producing magnetic recording medium

InactiveUS20070026141A1Facilitate immigrationSuppress base film breakageVacuum evaporation coatingSputtering coatingGas phaseEngineering
The present invention provides an apparatus and a method for producing a magnetic recording medium, which are free from base film breakage, capable of running a base film stably during a vapor deposition preparation stage and a vapor deposition step, and excellent in production efficiency. The production apparatus comprises a supply roll 14 for delivering a non-magnetic substrate 1, a rotary cooling drum 20, a crucible 17 housing a vapor deposition material 18, a maximum incident angle regulating mask 21A for regulating a maximum incident angle of an evaporated vapor deposition material to the non-magnetic substrate, a minimum incident angle regulating mask 21B for regulating a minimum incident angle, a pair of edge portion regulating masks 21C and 21D for regulating deposition on both edges in a width direction of the non-magnetic substrate 1 surface, a shutter 23 capable of opening and closing an aperture among masks 21A, 21B, 21C, and 21D, and a winding roll 16, wherein the edge portion regulating masks 21C and 21D are provided in such a manner as to keep a distance dA between ends on upstream side of the edge portion regulating masks and the cooling drum 20 larger than a distance dB between ends on downstream side of the edge portion regulating masks and the cooling drum 20.
Owner:TDK CORPARATION

High-limestone-flour-adulterate-amount composite enhanced grinding aid for cement and preparation method of high-limestone flour-adulterate amount composite enhanced grinding aid

The invention relates to a high-limestone-flour-adulterate-amount composite enhanced grinding aid for cement and a preparation method of the high-limestone-flour-adulterate-amount composite enhanced grinding aid. The preparation method comprises the following steps that 1, materials including 18%-25% of triethanolamine, 8%-15% of triisopropanolamine, 20%-28% of ethanediol, 8%-12% of molasses, 4%-8% of polycarboxylate superplasticizer, 6%-10% of sodium sulfate, 5%-8% of glacial acetic acid and 2%-24% of water are taken; 2, the water is poured into an agitator kettle, and sodium sulfate is added to be stirred till sodium sulfate is completely dissolved; 3, glacial acetic acid is added to be completely dissolved, triethanolamine, triisopropanolamine, ethanediol, molasses and polycarboxylate superplasticizer are sequentially added after glacial acetic acid is dissolved, stirring continues to be carried out for 20-30 minutes, and the high-limestone flour-adulterate amount composite enhanced grinding aid is obtained. The high-limestone-flour-adulterate-amount composite enhanced grinding aid has the advantages that cement particles are prevented from clustering, and the cement particles are kept in a high homodisperse state; the strength of an interfacial transition zone is increased, and the strength of the cement is further increased; the grinding aiding efficiency of the grinding aid is improved.
Owner:WUHAN UNIV OF TECH

Super junction device and manufacturing method thereof

The invention discloses a super junction device, grooves of a super junction structure are of a lateral inclined structure, the doping concentration of N-type epitaxial layers are distributed in a stepped mode, and P-type columns are formed of a plurality of layers of P-type epitaxial layers which are filled in the grooves in an overlapped mode; and the doping concentration of the P-type epitaxiallayers of the P-type columns is decreased successively from bottoms to tops of the grooves. A protective epoxy film wraps around the circumferential side of a current flow region; and the N-type epitaxial layer at the interface of the protective epoxy film and the oxide film epitaxial layer of the N-type epitaxial layer of a terminal region internally comprises a top region with the reduced N-type doping concentration, and the top region can enhance the lateral depletion capacity of the N-type column at the interface of the oxide film epitaxial layer. The invention further discloses a manufacturing method of the super junction device. According to the super junction device, the charge balance between the P-type columns and N-type columns of the super junction structure with the inclined grooves can be improved, the longitudinal voltage endurance capability of the device is improved, and the source leakage breakdown voltage of the device is increased; and the lateral voltage bearing capacity of a device terminal can further be improved, and reliability of the device is improved.
Owner:SHENZHEN SANRISE TECH CO LTD
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