48results about How to "Drain current increases" patented technology

A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions of the well are covered by a first insulator (503) having a first thickness. A second well (504) of the opposite conductivity type is intended to contain the transistor source (506) of the first conductivity type; portions of the second well are covered by a second insulator (507) thinner than the first insulator. The first and second wells form a junction (505) that terminates at the second insulator (530a, 530b). The method deposits a photoresist layer (510) over the wafer, which is patterned by opening a window (510a) that extends from the drain to the junction termination. Next, ions (540) of the first conductivity type are implanted through the window into the first well; these said ions have an energy to limit the penetration depth (541) to the first insulator thickness, and a dose to create a well region (560) of high doping concentration adjacent to the junction termination (530a).

A semiconductor device is provided which includes: semiconductor pillars which include impurity diffused layers, each semiconductor pillar having a width which allows full depletion of a semiconductor forming each semiconductor pillar, the impurity diffused layers being electrically connected to each other; and a common gate section which covers side faces of the pillars.

Provided are a CMOS transistor capable of meeting miniaturization requirements and reliability requirements and a manufacturing method thereof. A buried channel type PMOS transistor is arranged only in the CMOS transistor 100B corresponding to the high voltage, a surface channel type NMOS transistor is formed in the low voltage NMOS region LNR and a high voltage NMOS region HNR, and a surface channel type NMOS transistor is formed in the low voltage PMOS region LPR. Surface channel type PMOS transistor.

The invention discloses a GaN heterojunction HEMT (High Electron Mobility Transistor) device, belonging to the technical field of semiconductor devices. The GaN heterojunction HEMT device comprises a substrate and an InAIN/GaN heterojunction, wherein the InAIN/GaN heterojunction is positioned on the surface of the substrate; the surface of an InAIN layer is provided with a grid electrode, a source electrode and a drain electrode; and the drain electrode and the surface of the InAIN layer form ohmic contact, while the source electrode and the surface of the InAIN layer form Schottky contact. The GaN heterojunction HEMT device disclosed by the invention has the advantages that the Schottky contact is adopted at the source electrode, the electric field in GaN under the source electrode is uniformly distributed due to a good appearance characteristic, the electron injection of the source electrode is effectively restrained, and the current leakage of GaN and collision ionization and current leakage of the grid electrode caused by the current leakage are reduced, so that the off-state puncture voltage of the device is improved; the drain electrode adopts ohmic contact still, so that the positive on resistance of the device is reduced as low as possible, and better positive current driving capability of the device is ensured; in addition, the GaN heterojunction HEMT device is compatible to the traditional process, simultaneously the distance between the grid electrode and the source electrode can be very short, and the wafer occupying area is smaller, so that lower cost of the device is ensured.

The invention discloses a lateral diffusion eGaN HEMT device integrating a reverse diode and an embedded drain electrode field plate. The device comprises a GaN buffer layer, an AlGaN barrier layer, agate electrode, an under-gate insulating layer, a source electrode, a source electrode extension section, a source electrode field plate, an MIS schottky diode extension section, an MIS schottky diode insulating layer, a p-type GaN or groove, a drain electrode, a passivation layer and an AlN staggered-layer drain electrode embedded field plate, wherein the MIS schottky diode insulating layer is prepared in the middle region, towards the MIS schottky diode extension section and the AlGAN barrier layer surface, of the source electrode field plate; the side, close to the drain electrode, of thediode adopts the p-type GaN or groove, so that the breakdown characteristic of the device is improved; the embedded staggered-layer field plate is adopted below the drain electrode, so that anti-breakdown capability of the drain electrode to the substrate is improved; the design of the staggered layer is suitable for the gradual change distribution of the drain electrode electric field from rightto left, so that the breakdown characteristic of the device is improved; and the source electrode field plate is extended, the gate electrode is wrapped, the MIS schottky diode is formed on the gate drain side, and the diode is made into a block isolation mode, so that the drain electrode current is greatly improved.

The invention provides a thin film transistor, which comprises a grid, a grid insulating layer, a channel layer, a source electrode and a drain electrode, wherein the grid is arranged on a substrate; the grid insulating layer is covered on the grid; the channel layer is arranged on the grid insulating layer above the grid; the longitudinal section of the channel layer can be of a wave shape; and the source electrode and the drain electrode are arranged on the channel layer; in addition, the longitudinal section of the channel layer can be flat in surface, and the source electrode and the drain electrode at two sides covered on the channel layer are in nonlinear line list structures.

The invention discloses a 4H-SiC metal-semiconductor field effect transistor with a double-sunken buffer layer. The 4H-SiC metal-semiconductor field effect transistor comprises a 4H-SiC semi-insulating substrate, a P type buffer layer and an N type channel layer from bottom to top, wherein a source electrode cap layer and a drain electrode cap layer are respectively arranged on two sides of the N type channel layer; a source electrode and a drain electrode are respectively arranged on the surfaces of the source electrode cap layer and the drain electrode cap layer; a gate electrode is formed on one side, close to the source electrode cap layer, above a channel; grooves are arranged on the upper end face of the P type buffer layer and under a gate source and a gate leakage. The 4H-SiC metal-semiconductor field effect transistor has the advantages that the output drain electrode current is obviously improved, and the breakdown voltage is stable.

The invention discloses a 4H-SiC metal semiconductor field effect transistor with a slope-shaped grid. The 4H-SiC metal semiconductor field effect transistor comprises a 4H-SiC semi-insulating substrate, a P-type buffer layer and an N-type channel layer from bottom to top, a source electrode cap layer and a drain electrode cap layer are arranged on the surface of the N-type channel layer, a source electrode and a drain electrode are arranged on the surface of the source electrode cap layer and the surface of the drain electrode cap layer respectively, a slope-shaped groove inclined towards one side of the source electrode cap layer is formed in the upper end face of the N-type channel layer, the slope-shaped grid is arranged is arranged in the slope-shaped groove, the lower end face of the slope-shaped grid is matched with the slope-shaped groove, the upper end face of the slope-shaped grid is parallel to the upper end face of the N-type channel layer, and the distance between the slope-shaped grid and the source electrode cap layer is smaller than that between the slope-shaped grid and the drain electrode cap layer. The field effect transistor has the advantages of being high in drain electrode output current and excellent in frequency property.

The invention belongs to the technical field of field effect transistors, and particularly discloses a preparation method for a metal semiconductor field effect transistor with wide channels and deep recesses. The preparation method for the metal semiconductor field effect transistor with the wide channels and deep recesses settles the problems in prior art and has advantages of realizing simple manufacture process, enlarging an output current and a breakdown voltage, and improving frequency characteristic. The preparation method comprises the steps of cleaning a semi-insulating substrate; realizing epitaxial growth of a P-type buffer layer; realizing epitaxial growth of an N-type channel layer on the P-type buffer layer; realizing epitaxial growth of an N<+> cap layer on the N-type channel layer; preparing an isolation region and an active region; preparing a source electrode and a drain electrode; performing lithography and etching on the N<+> between the source electrode and the drain electrode, thereby forming a high-gate area; manufacturing a gate electrode; and manufacturing an electrode pads, thereby finishing device preparation.

The invention discloses a ferroelectric material reconfigurable field effect transistor. The transistor includes a channel; a drain electrode arranged at one end of the channel; a source electrode arranged at the other end of the channel; a gate dielectric buffer layer arranged at the outer side of the channel, a ferroelectric material layer which wraps the outer side of the gate dielectric bufferlayer, a control gate and a polar gate which are arranged at the source electrode end and the drain electrode end respectively and at the outer side of the ferroelectric material layer, and an innerside wall and an outer side wall which are used for electrically isolating the control gate and the polar gate from the source electrode and the drain electrode. The ferroelectric material layer arranged at the outer side of the gate dielectric buffer layer can generate the polarized charges at the channel below the ferroelectric material layer, so that the control capability of the gate to the channel is improved, the turn-on voltage under a same gate voltage is increased, the sub-threshold swing of a device is reduced, and the static power consumption of the device is reduced. The gate dielectric buffer layer isolates the channel from the ferroelectric material, prevents the mutual diffusion of the channel and the ferroelectric material, and does not affect the polarization characteristics of the ferroelectric material layer.

A method of manufacturing a semiconductor device having a field effect transistor with improved current driving performance (increase of drain current) of a field effect transistor comprising the steps of ion implanting a group IV element from the main surface to the inside of a silicon layer as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer as a semiconductor substrate to form the semiconductor region being aligned with the gate electrode.

The invention discloses a semiconductor component, a manufacturing method thereof and an operating method thereof. The semiconductor component includes a metal oxide semiconductor transistor, a resistor and a Zener diode. The metal oxide semiconductor transistor includes a grid electrode, a source electrode and a drain electrode. One end of the resistor is electrically connected with the drain electrode, and the resistor has a resistance value high enough to enable most current to flow through the metal oxide semiconductor transistor. The Zener diode includes a cathode and an anode, the cathode is electrically connected with the grid electrode and the other end of the resistor, and the anode is electrically connected with a grid electrode of a substrate.

The invention belongs to the technical field of field effect transistors, and especially discloses a metal semiconductor field effect transistor with wide-channel deep sags. The invention aims to provide a metal semiconductor field effect transistor with wide-channel deep sags which has higher output current and breakdown voltage and better frequency characteristic. The technical scheme adopted is as follows: a 4h-SiC half-insulating substrate, a P-type buffer layer and an N-type channel layer are arranged from top to bottom; a source cap layer and a drain cap layer are respectively arranged at the two sides of the N-type channel layer; a gate electrode is arranged in the middle of the N-type channel layer and close to the side where the source cap layer is arranged; the gate electrode enables a left channel sag area and a right channel sag area to be formed at the two sides of the N-type channel layer; the depths of the left channel sag area and the right channel sag area are 0.15-0.25 microns; the width of the left channel sag area is 0.5 microns, and the width of the right channel sag area is 1 micron; and a high-gate area is formed between the channel surface and the gate electrode.

The invention provides a GaN-based P-type grid-enhanced type HEMT device and a preparation method thereof. The device comprises a substrate layer, a channel layer, a barrier layer, a grid electrode and a drain electrode; the channel layer is arranged on the substrate layer, the barrier layer is arranged on the channel layer, the grid electrode penetrates through the barrier layer, the drain electrode is arranged on the barrier layer, and P-type diamond is adopted as the grid electrode. The preparation method of the device comprises the following steps that 1, GaN deposition is performed on the substrate layer to form the channel layer; 2, an AlGaN layer grows on the channel layer; 3, a layer of the p-type diamond grows on the barrier layer to form the grid electrode; 4, a source electrode and the drain electrode are formed on the portions, on the two sides of the grid electrode, of the barrier layer respectively. According to the GaN-based P-type grid-enhanced type HEMT device and the preparation method thereof, the P-type diamond grid electrode is adopted, an energy band can be improved, the enhanced characteristic is achieved by using up channel electrons when the grid voltage is 0, regulation on threshold voltage of the device can be achieved, and small grid currents are kept while drain currents are increased.

The invention belongs to the technical field of field effect transistors, and especially discloses a field effect transistor with a three-sag structure and a preparation method thereof. The invention aims to provide a field effect transistor with a three-sag structure which has wide-channel deep sags and has higher output current and breakdown voltage and better frequency characteristic, and a preparation method thereof. The technical scheme adopted is as follows: a 4h-SiC half-insulating substrate, a P-type buffer layer and an N-type channel layer are arranged from top to bottom; a source cap layer and a drain cap layer are respectively arranged at the two sides of the N-type channel layer; a source electrode and a drain electrode are respectively arranged on the surfaces of the source cap layer and the drain cap layer; a ladder-shaped gate electrode is arranged in the middle of the N-type channel layer and close to the side where the source cap layer is arranged; and a left channel and a right channel are respectively formed at the two sides of the gate electrode and the N-type channel layer.

The invention discloses a carborundum semiconductor element and a manufacture method for the same. The manufacture method comprises steps of arranging a channel control area, and enabling the channel control area to have a foreign matter concentration distribution which progressively increases from a first doped boundary, achieves a maximum value between the first doped boundary and a second doped boundary, and progressively decreases toward the second doped boundary. The manufacture method enables the carborundum semiconductor element to reduce the conduction resistor and improve the drain current without sacrificing the critical voltage.

The invention discloses a charge pump with a wide locking range and low current mismatch. The charge pump comprises a charge pump biasing circuit, a charge pump core circuit and the like. According to the invention, the PMOS tube M9 of the charge pump biasing circuit is connected through a diode, and the grid electrode of the PMOS tube M8 is connected with the output end of the charge pump, so that the problem that the discharge current is small when the output voltage of the charge pump is low is solved in the discharge state, and the voltage dynamic range of the output end of the charge pump is enlarged; an error amplifier op1 in a charge pump core circuit adopts unit gain connection, so that a charge sharing effect can be suppressed at the moment of charge/discharge conversion; and the PMOS tube M17 and the PMOS tube M10 respectively form a feedback compensation circuit with an error amplifier op2, and the voltage of the output end of the charge pump in a charging state is gradually increased so as to reduce the grid voltage of the PMOS tube M17 and the grid voltage of the PMOS tube M10 and increase the charging current, so that the dynamic range of the voltage of the output end of the charge pump is further enlarged so as to achieve the charge pump with wide locking range and low current mismatch.

The invention relates to a 4H-SiC metal semiconductor field effect transistor having double high gates. The 4H-SiC metal semiconductor field effect transistor comprises a 4H-SiC semi-insulating substrate, a P-type buffer layer and an N-type channel layer which are arranged from the bottom to the top in turn. The two sides of the N-type channel layer are respectively provided with a source cap layer and a drain cap layer. The surfaces of the source cap layer and the drain cap layer are respectively provided with a source electrode and a drain electrode. A gate electrode is formed on one side which is close to the source cap layer and arranged above the N-type channel layer. A left channel concave region, a right channel concave region and a middle channel concave region are formed at the left side, the right side and the middle of the N-type channel by the gate electrode. A left high gate region and a right high gate region are formed between the surface of the channel and the gate electrode. The advantages of the 4H-SiC metal semiconductor field effect transistor are that drain current is enhanced, breakdown voltage is enabled and the frequency characteristics are improved.

The invention provides a semiconductor structure and a formation method thereof. The formation method of the semiconductor structure includes providing a substrate; forming a projecting grid on the surface of the substrate; forming gate medium layers on the surfaces of the side walls of the grid; forming a channel layer on the surface of the grid medium layer; forming a medium layer on the surface of the substrate; forming a first through hole in the medium layer on each side of the grid, wherein a part of the medium layer is arranged between the first through hole and the channel layer; and forming back grids in the first through holes. The semiconductor structure formed by adopting the above method has a comparatively large channel length and can adjust the threshold voltage of a transistor by exerting voltage on the channel layer through the back grids.