Semiconductor device and its manufacture

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, transistors, electrical components, etc., can solve problems such as reducing and reducing carrier mobility

Inactive Publication Date: 2002-12-11
MITSUBISHI ELECTRIC CORP
View PDF0 Cites 17 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, in the surface channel type, the channel is formed directly under the gate insulating film, so the mobility of carriers may be reduced due to a strong vertical electric field
In addition, because of the strong electric field, the reliability under hot carrier stress or the reliability under bias temperature stress (NBTI: Negative Bias Temperature Instability) is significantl

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor device and its manufacture
  • Semiconductor device and its manufacture
  • Semiconductor device and its manufacture

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0088] [A-1. Manufacturing method]

[0089] A method of manufacturing a semiconductor device having a CMOS transistor 100A and a CMOS transistor 100B as a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIGS. 1 to 9 . The structures of the CMOS transistor 100A corresponding to the low voltage and the CMOS transistor 100B corresponding to the high voltage are shown in the section explaining the final process. Figure 9 middle.

[0090] First, as shown in FIG. 1, an element isolation insulating film 20 is selectively formed in the surface of a silicon substrate 10, and a low-voltage NMOS region LNR and a low-voltage PMOS region LPR for forming a low-voltage NMOS transistor and a low-voltage PMOS transistor are defined. , specifying the high voltage NMOS region HNR and the high voltage PMOS region HPR forming the high voltage NMOS transistor and the high voltage PMOS transistor.

[0091] Corre...

Embodiment 2

[0120] [B-1. Manufacturing method]

[0121] A method of manufacturing a semiconductor device having a CMOS transistor 200A and a CMOS transistor 200B as a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIGS. 10-13. The structures of the CMOS transistor 200A corresponding to the low voltage and the CMOS transistor 200B corresponding to the high voltage are shown in the section explaining the final process. Figure 13 middle. with Figure 1- Figure 9 Structures having the same manufacturing methods of the low-voltage corresponding CMOS transistor 100A and the high-voltage corresponding CMOS transistor 100B described above are assigned the same reference numerals, and repeated explanations are omitted.

[0122] First, as shown in FIG. 10, a gate insulating film 41 is formed on the entire surface of the low-voltage NMOS region LNR and the low-voltage PMOS region LPR on the silicon substrate 10 t...

Embodiment 3

[0145] [C-1. Manufacturing method]

[0146] use Figure 14-21 A method of manufacturing a semiconductor device having a CMOS transistor 300A and a CMOS transistor 300B as a method of manufacturing a semiconductor device according to Embodiment 3 of the present invention will be described. The structures of the CMOS transistor 300A corresponding to the low voltage and the CMOS transistor 300B corresponding to the high voltage are shown in the section explaining the final process. Figure 21 middle. with Figure 1- Figure 9 Structures having the same manufacturing methods of the low-voltage corresponding CMOS transistor 100A and the high-voltage corresponding CMOS transistor 100B described above are assigned the same reference numerals, and repeated explanations are omitted.

[0147] First, if Figure 14 1 and 2, a gate insulating film 41 is formed on the entire surface of the low voltage NMOS region LNR and the low voltage PMOS region LPR on the silicon substrate 10. Gate ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Login to view more

Abstract

Provided are a CMOS transistor capable of meeting miniaturization requirements and reliability requirements and a manufacturing method thereof. A buried channel type PMOS transistor is arranged only in the CMOS transistor 100B corresponding to the high voltage, a surface channel type NMOS transistor is formed in the low voltage NMOS region LNR and a high voltage NMOS region HNR, and a surface channel type NMOS transistor is formed in the low voltage PMOS region LPR. Surface channel type PMOS transistor.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a CMOS transistor and a manufacturing method thereof. Background technique [0002] In forming a CMOS (complementary MOS) transistor used after combining an N-channel MOSFET (hereinafter referred to as an NMOS transistor) and a P-channel MOSFET (hereinafter referred to as a PMOS transistor), although an NMOS transistor and a PMOS transistor are formed, at this time, It is necessary to form gates that conform to the respective characteristics. [0003] For MOS transistors with a gate length of 0.25-0.35 microns, surface channel type is used in NMOS transistors, and buried channel type is used in PMOS transistors. For both types, phosphorus (P) introduced into the gate can be used. ) polysilicon as impurities. [0004] However, it is difficult to miniaturize the PMOS transistor using a buried channel type in which a channel is formed inside the substrat...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L27/092H01L21/8234H01L21/8238H01L27/088
CPCH01L21/823807H01L21/823842H01L21/823857H01L27/092
Inventor 佐山弘和西田征男太田和伸尾田秀一
Owner MITSUBISHI ELECTRIC CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap