Semiconductor device and its manufacture

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, transistors, electrical components, etc., can solve problems such as reducing and reducing carrier mobility
CN1384547AInactive Publication Date: 2002-12-11MITSUBISHI ELECTRIC CORP
0 Cites 17 Cited by

Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
MITSUBISHI ELECTRIC CORP
Publication Date
2002-12-11
Estimated Expiration
Not applicable · inactive patent

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

Provided are a CMOS transistor capable of meeting miniaturization requirements and reliability requirements and a manufacturing method thereof. A buried channel type PMOS transistor is arranged only in the CMOS transistor 100B corresponding to the high voltage, a surface channel type NMOS transistor is formed in the low voltage NMOS region LNR and a high voltage NMOS region HNR, and a surface channel type NMOS transistor is formed in the low voltage PMOS region LPR. Surface channel type PMOS transistor.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a CMOS transistor and a manufacturing method thereof. Background technique

[0002] In forming a CMOS (complementary MOS) transistor used after combining an N-channel MOSFET (hereinafter referred to as an NMOS transistor) and a P-channel MOSFET (hereinafter referred to as a PMOS transistor), although an NMOS transistor and a PMOS transistor are formed, at this time, It is necessary to form gates that conform to the respective characteristics.

[0003] For MOS transistors with a gate length of 0.25-0.35 microns, surface channel type is used in NMOS transistors, and buried channel type is used in PMOS transistors. For both types, phosphorus (P) introduced into the gate can be used. ) polysilicon as impurities.

[0004] However, it is difficult to miniaturize the PMOS transistor using a buried channel type in which a channel is formed inside the substrat...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More