Novel 3D NAND memory device and method of forming same

Abstract

In the memory device, a lower memory cell string including a first channel structure, a plurality of first word line layers, and a first insulating layer is formed over a substrate. The first channelstructure extends from the substrate and passes through the first word line layer and the first insulating layer. Inter-stack contacts are formed over the lower memory cell string and coupled to the first channel structure. An upper memory cell string is formed over the inter-stack contacts. The upper memory cell string includes a second channel structure, a plurality of second word lines, and a second insulating layer. The second channel structure passes through the second word line and the second insulating layer and extends into the inter-stack contacts and further laterally into the secondinsulating layer. A channel dielectric region of the second channel structure is above the inter-stack contacts.

Description

Background technique [0001] As the critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technology, designers have been looking for ways to stack multiple planes of memory cells to achieve higher storage capacities and achieve lower cost-per-bit technology. [0002] The inventive concept relates to a nonvolatile memory device, and more particularly to a vertical type 3D NAND memory device in which a channel structure extends in a vertical direction. As the size of electronic products can be gradually reduced, these products may be required to perform data processing at a higher capacity. Accordingly, the degree of integration of semiconductor memory devices used in electronic products can be increased. A method of increasing the integration of semiconductor memory devices may involve nonvolatile memory devices having a vertical structure instead of a planar transistor structure. [0003] Compared with the planar transistor structu...

AI Technical Summary

Problems solved by technology

[0003] Compared with the planar transistor structure, the vertical structure of 3D NAND memory device involves more critical and complex manufacturing process

As 3D NAND memory devices move toward higher density configurations with more memory cell layers at a lower cost per bit, improvements to the structure and its fabrication methods become increasingly challenging

Images