Semiconductor device and method of manufacturing the same

Abstract

Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns including a silicon-oxide-based material are formed on sidewalls of the wiring, and contact patterns and spacers on the sidewalls thereof for defining contact hole regions are formed on the wiring. The contact holes contact surfaces of the third insulating film patterns and pass through the first insulating film. Thus, the thickness of a second insulating film pattern used in the wiring can be minimized, thereby increasing a gap-fill margin between the wiring. A parasitic capacitance between the wiring can be reduced because silicon oxide spacers with a low dielectric constant are formed on sidewalls of the wiring.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a Divisional of U.S. patent application Ser. No. 10 / 719,624, filed on Nov. 20, 2003, now pending, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 2003-03359, filed on Jan. 17, 2003, the contents of which are herein incorporated by reference in their entirety for all purposes.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates generally to a semiconductor device, and more particularly, to a dynamic random access memory (DRAM) device and a method of manufacturing the same. [0004] 2. Description of the Related Art [0005] As the technology for manufacturing semiconductor devices has progressed and become more developed, because of increasing demands for products that utilize memory devices, there has been a demand to provide larger capacity memory devices. To help meet this demand, the integration density of a DRAM device whose memory cell is comp...

AI Technical Summary

Benefits of technology

[0031] According to the present invention, the contact patterns and contact spacers, which are composed of materials having etching selectivities relative to the silicon oxide based materials, are formed on the wiring. Then, using the contact patterns and the contact spacers as etching masks, the insulating films composed of silicon oxide based materials are etched to form the contact holes between the wiring. Since the contact patterns and contact spacers protect the conductive film patterns of the wiring during an etching process for forming the contacts, a thickness of the second insulating film pattern of the wiring can be minimized to decrease the height of the wiring. Therefore, the aspect ratios of the wiring can be reduced to increase a gap-fill margin between the wiring.

[0032] In addition, since the contact hole between the wiring, e.g., the storage node contact hole, is not formed by a self-aligned contact etching process, a shoulder margin of the wiring can be maintained to prevent an electrical short-circuit between the wiring and the contact plug formed in the contact hole.

[0033] Additionally, a parasitic capacitance between the wiring or between the wiring and the contact plug can be reduced because the spacers, which are composed of the silicon oxide based materials with low dielectric constants, are formed on the sidewalls of the wiring.

Problems solved by technology

As a result, the formation of a minute contact hole may become very difficult through conventional methods of forming contact holes.

If the thickness of the bit line mask layer is reduced to settle this problem, bit line notching may occur due to a low etching selectivity between the photoresist and the silicon nitride.

However, in the above methods, a reduction in the thickness of the bit line mask layer may limit the gap-fill margin of an interlayer dielectric film or decrease the shoulder margin of a bit line during an etching process for a self-aligned contact.

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