22results about How to "Good etching" patented technology

The invention discloses a manufacturing method of a super junction device. The manufacturing method comprises the following steps: growing a first epitaxial layer; a plurality of trench gates are formed in a first epitaxial layer, gate conductive material layers outside gate trenches of the trench gates are all removed, and the top surfaces of the gate conductive material layers in the gate trenches are flat, so that the formation process of a subsequent second trench is ensured to be realized. And forming a well region and performing annealing. And performing photoetching and etching to form a plurality of second grooves, wherein the first epitaxial layer between the second grooves is used as a first conductive type column. And growing a second conductive type doped second epitaxial layer in the second groove, completely removing the second epitaxial layer outside the second groove, flattening the surface of the second epitaxial layer in the second groove, and forming a second conductive type column by the second epitaxial layer filled in the second groove. And a subsequent front process is completed, and a thermal process is set according to the requirement for controlling mutual diffusion of PN impurities of the super junction structure. And completing a back process. According to the invention, mutual diffusion of PN impurities of the super junction structure can be effectively controlled.

The invention discloses a semiconductor structure processing method, a semiconductor structure and a semiconductor processing device. The processing method comprises the steps that a substrate is provided and comprises a base layer arranged on the substrate, the base layer is provided with a slope structure, the side portion of the base layer gradually extends outwards in the direction from the top surface to the substrate, the slope structure is covered with a cut-off layer, and a dielectric layer is arranged on the cut-off layer; starting a source radio frequency and a bias radio frequency, introducing a first etching gas, and etching the dielectric layer until the third-type hole exposes the cut-off layer; reducing the power of bias radio frequency, so that the openings of the first type of holes, the second type of holes and the third type of holes are laterally etched; and second etching gas is introduced, the cut-off layer exposed by the third type of holes is etched, and the flow of the second etching gas is linearly increased at the slope k along with the etching time until the cut-off layer of the third type of holes is etched to the preset depth. By controlling the allowance of the cut-off layer in the through holes with different depths and different depth-to-width ratios, the process window of the subsequent process of striking the cut-off layer is expanded.

The invention relates to a one-dosage type copper-molybdenum display etching solution and a preparation method and application thereof. The etching liquid comprises the following components in parts by weight: 5-15 parts of hydrogen peroxide; 10 to 15 parts of organic acid; 8-12 parts of an organic base; 0.008 to 0.07 part of a chelating agent; 0.002 to 0.07 part of a corrosion inhibitor; 0.04 to 0.3 part of a surfactant; 0.1 to 0.6 part of a hydrogen peroxide stabilizer; and 65-73 parts of ultrapure water. The chelating agent and the corrosion inhibitor in the etching solution are jointly adsorbed on the metal surface, the corrosion inhibitor and the chelating agent can form intermolecular hydrogen bonds to obtain a product with larger molecular volume, the product is adsorbed on the metal surface to generate a protective isolation layer, and meanwhile, the contained delocalized large pi bonds and nitrogen atoms can provide electron pairs for empty orbits of metal, so that the metal surface is protected. And coordination bonds are formed to be adsorbed on the metal surface to form a compact adsorption film, so that the corrosion of the metal is effectively inhibited, and the taper angle and the etching morphology of the etched metal are stabilized.

The invention discloses a manufacturing method of a super junction device. The manufacturing method comprises the following steps: growing a first epitaxial layer; and injecting a first P-type impurity into a surface region of the first epitaxial layer in a first selected region, wherein the first selected region at least comprises a partial region, close to the transition region, of the terminal region. And forming a trench gate. And forming a well region and performing annealing. And forming a second groove. And growing a P-type doped second epitaxial layer in the second groove, removing the second epitaxial layer outside the second groove, and flattening the surface of the second epitaxial layer in the second groove. And completing a subsequent front process and setting a thermal process according to the requirement of controlling PN impurity mutual diffusion of the super junction structure, wherein the subsequent front process comprises the step of forming a protective epoxy film covering the inner side region of a cut-off region of the transition region and the terminal region. And completing a back process. According to the invention, mutual diffusion of PN impurities of the super junction structure can be effectively controlled, the reliability of a product can be improved, PN balance of a terminal region can be improved, BVdss of a device and consistency of the BVdss are improved, and the EAS capability is improved.

This invention provides an image sensor and its fabrication method. The projections of multiple photodiodes in the photodiode group on a substrate surround the projection of a floating diffuser on the substrate. Intra-group deep trench isolation is provided between adjacent photodiodes within the photodiode group. The intra-group deep trench isolation includes a linear pattern structure obtained by removing the intersection region of a first line trench isolation along a first direction and a second line trench isolation along a second direction. The intra-group deep trench isolation removes the intersection region, and the projection of the intersection region on the substrate covers the projection of the floating diffuser on the substrate. That is, the intra-group deep trench isolation is not provided in the intersection region of the line trench isolation on the substrate above the floating diffuser to avoid damaging the floating diffuser and causing white pixel problems, thus improving pixel quality. The deeper intra-group deep trench isolation reduces or avoids crosstalk and overflow between photodiodes.

The invention relates to the technical field of etching solutions, in particular to the field of IPC C23F1, and more particularly relates to a Cu-Mo alloy multi-film structure etching solution composition. The etching solution comprises the following components in percentage by weight: 14-25% of hydrogen peroxide, 1-6% of a chelating agent, 0.5-4% of an etching agent, 0.1-3% of a regulator, 0.01-1% of an inhibitor, 0.02-6% of a stabilizer and the balance of water. The excellent etching performance conditions are as follows: CD-loss is 0.4-0.55 [mu] m, Taper angle is 40-50 DEG C, no residue and no crack exist, IGZO damagge # imgabs 0 # is below, the highest copper load is 3000 ppm or above, and the service time is 12 hr or above.

The invention relates to a vertically stacked red, green and blue full-color carrier chip for a microLED display panel. The vertically stacked red, green and blue full-color carrier chip comprises a temporary wafer; and a plurality of LED stacks arranged on the temporary wafer, each of the plurality of LED stacks including a light emitting portion stacked in a vertical direction by a bonding layer, the plurality of LED stacks forming a short channel in a partial region, and emitting only a specific color by current to the light emitting portion where the short channel is not formed, the short channels include a first short channel formed so as to correspond to the width of the light-emitting part, and a second short channel formed so as to penetrate through the light-emitting part.

The invention discloses a copper-titanium laminated metal etching solution with long service life and an etching method, and the copper-titanium laminated metal etching solution comprises the following raw materials in percentage by mass: 1-6% of hydrogen peroxide, 5-9% of organic acid, 3-7% of organic salt, 1-3% of hydrogen peroxide stabilizer, 0.5-0.9% of fluorine ion source, 0.01-0.6% of metal corrosion inhibitor, 1-5% of complexing agent and the balance of water. Under the conditions that the hydrogen peroxide content is low and inorganic acid is not contained, a good etching effect is achieved, along with gradual increase of the copper ion concentration in the etching liquid, the etching morphology still has a stable etching taper angle and CD bias, and the long service life is achieved.

A slide glass jig for LED chip dry etching relates to the technical field of semiconductors, and comprises a shell mechanism provided with two protection mechanisms, a master control mechanism arranged in the shell mechanism and used for controlling the two protection mechanisms to work, and two cooling mechanisms arranged at the lower ends of the two protection mechanisms respectively, the buffer mechanism is used for providing helium for the two cooling mechanisms and preventing the wafer from being damaged due to too large input air pressure; according to the equipment, the carrying table can be stored in the equipment, the carrying table is prevented from being directly exposed, and the carrying table is effectively protected; according to the equipment, when a wafer is etched, the carrying table can be lifted out of the equipment, the operation is simple, and the practicability is high; the equipment can be used for uniformly and effectively cooling the carrying table, so that the utilization rate of the equipment is improved, and meanwhile, the smooth dry etching of the LED chip is ensured.

The invention relates to a buffer oxidation etching solution for thinning a quartz wafer. The buffer oxidation etching solution comprises 10%-20% of hydrofluoric acid, 15%-35% of ammonium fluoride, 0.1%-5% of an alcohol compound, 0.1%-2% of organic acid and the balance ultrapure water. The etching solution is used for maintaining a proper etching rate for the quartz wafer, the etched quartz wafer has good morphology and etching roughness, and triangular pyramid structure protrusions existing on the surface of the wafer after conventional BOE etching are improved.

The invention relates to the technical field of sodium ion batteries, in particular to a method for reactivating a failed hard carbon negative electrode material and application thereof, and the method comprises the following steps: putting a failed hard carbon negative electrode sheet into ethylene glycol dimethyl ether for ultrasonic cleaning and then drying; and placing the dried hard carbon negative electrode plate in a mold, and carrying out reactivating treatment by using cold plasma to obtain an activated hard carbon negative electrode plate. Reactivation treatment of the failed hard carbon electrode plate is achieved through cold plasma, the failed hard carbon electrode plate is cleaned with ethylene glycol dimethyl ether, residual sodium salt and glass fibers on the surface of the electrode plate are removed, cold plasma treatment is facilitated, and direct etching of a solid electrolyte layer is facilitated; harmful gas and waste liquid are not generated in the process of etching the surface of the electrode plate by adopting the gas-phase plasma, so that the problems of high cost, energy consumption, harmful gas emission, acid waste, extra treatment cost and the like caused by the recovery process of the failed hard carbon electrode plate as a negative electrode material are solved, and the economic benefit is favorably improved.

The invention discloses a modified preparation method of a mosaic mesophase asphalt-based silicon-carbon composite electrode material, using a petroleum-based mosaic mesophase asphalt as a carbon source and an oxygen-containing organosilicon compound as a silicon source, obtaining a preliminary composite product through hydrothermal reaction and magnesium thermal reduction, and then using calcium carbonate as a sacrificial layer, and the mosaic mesophase asphalt as both an outer coating layer and an inner core, to prepare a silicon-carbon composite electrode material with a "carbon-void-silicon-carbon" four-level core-shell structure. The structure of the mosaic mesophase asphalt allows lithium ions to be quickly embedded between carbon layers from all directions during high-current charge and discharge, and has a high rate performance. The first-cycle coulomb efficiency of the composite electrode material finally obtained is above 70%, the reversible specific capacity at a current density of 0.1C is above 550mAh / g, and the specific capacity at a high current density of 10C is above 400mAh / g, and it has the advantages of good conductivity, good rate performance, and stable cycle performance.

The invention relates to a circuit board manufacturing method, a circuit board and electronic equipment. The circuit board manufacturing method comprises the following steps: providing a substrate provided with a via hole; a first photosensitive film layer is formed on the substrate. The first photosensitive film layer comprises a first light shielding part and a first exposure part arranged around the first light shielding part. At least part of the first light shielding part covers the via hole, and at least part of the first exposure part covers the periphery of the hole opening of the via hole. And exposing and developing the first photosensitive film layer, retaining the first exposure part and removing the first light shielding part to form a first processing substrate. And performing electroplating treatment on the first processing substrate, so that a first metal layer is attached to the hole wall of at least part of the via holes. The circuit board manufacturing method is beneficial to reducing copper electroplating consumables in the electroplating process of the circuit board, the surface thickness of the circuit board is reduced, the uniformity of the circuit board is improved, and in addition, the thickness of an electroplating metal layer is ensured.

The invention belongs to the technical field of electro-catalytic materials, and discloses a water-corrugation-shaped polyoxosulfide self-supporting electrode and a preparation method and application of the water-corrugation-shaped polyoxosulfide self-supporting electrode. Foamed nickel is used as a substrate of a self-supporting electrode, after the foamed nickel is pretreated, the pretreated foamed nickel is immersed in a precursor solution containing potassium ferricyanide, soluble vanadium salt and soluble cobalt salt, nickel on the surface of the foamed nickel is etched into nickel ions through room-temperature ultrasound, the nickel ions are released into the precursor solution, and the self-supporting electrode is obtained. A multi-metal cation precursor solution is obtained; the method comprises the following steps: adding a sulfur source into a precursor solution of multi-metal ions under an ultrasonic condition, so that ferric ions, nickel ions and cobalt ions in the precursor solution of the multi-metal ions react with the sulfur source to form a multi-metal sulfide, and meanwhile, doping oxygen ions combined with vanadium ions into the multi-metal sulfide to generate a precursor self-supporting electrode; and performing Joule heating on the precursor self-supporting electrode to obtain the multi-metal oxysulfide self-supporting electrode.

The invention provides a groove type JFET device of a wide band gap material and a preparation method of the groove type JFET device. The device includes: a cell region trench; a cellular area platform; a plurality of transition region trenches; a plurality of transition zone platforms; the source region is formed at the top of the cellular region platform; the cell region gate region is formed in the epitaxial layer on the side wall and the bottom of the cell region groove, and the transition region gate region is formed in the epitaxial layer on the side wall and the bottom of the transition region groove; the source electrode metal covers the top of the source region; the cellular region gate metal covers the bottom of the cellular region groove, and the transition region gate first metal covers the bottom of the transition region groove; the cell region gate metal and the transition region gate first metal form interconnection at the bottom of the groove; the transition region gate second contact metal covers the top of the transition region platform and is arranged in a floating manner. The device is high in reliability and low in etching difficulty.

The present invention relates to a vertically stacked micro display panel, comprising: a back wafer having a plurality of CMOS electrode pads arranged on the upper surface thereof; a plurality of LED stacks each including a light emitting portion stacked in a vertical direction by a bonding layer, the plurality of LED stacks being arranged on the plurality of CMOS electrode pads; and a common electrode formed on the plurality of LED stacks, each of the plurality of LED stacks forming a short channel in a partial region, the short channel including a first short channel formed so as to correspond to the width of the light-emitting section, the first short channel including a second short channel formed so as to correspond to the width of the light-emitting section, the second short channel including a second short channel formed so as to correspond to the width of the light-emitting section, and the first short channel including a second short channel formed so as to correspond to the width of the light-emitting section, and the second short channel including a third short channel formed so as to correspond to the width of the light-emitting section. And a second short channel formed so as to pass through the light-emitting unit. According to the present invention, there is an effect of facilitating the formation of a short channel in a vertically stacked serial connection (tandem) structure.

A composition comprising octafluorocyclobutane, and comprising at least one of iodine and an iodine-containing perfluoroalkyl compound, the content of the aforementioned iodine and iodine-containing perfluoroalkyl compound being 1,000 mol ppm or less relative to the total molar amount of the composition.

The invention discloses a manufacturing method of a super junction device. The manufacturing method comprises the following steps: growing a first epitaxial layer; and injecting a first P-type impurity into a surface region of the first epitaxial layer in a first selected region, wherein the first selected region at least comprises a partial region, close to the transition region, of the terminal region. And forming a trench gate, removing the gate conductive material layer outside the gate trench of the trench gate, and enabling the top surface of the gate conductive material layer in the gate trench to be flat. And forming a well region and performing annealing. And forming a second groove. And growing a P-type doped second epitaxial layer in the second groove, completely removing the second epitaxial layer outside the second groove, and flattening the surface of the second epitaxial layer in the second groove. And a subsequent front process is completed, and a thermal process is set according to the requirement for controlling mutual diffusion of PN impurities of the super junction structure. And completing a back process. According to the invention, mutual diffusion of PN impurities of the super junction structure can be effectively controlled, PN balance of a terminal region can be improved, BVdss of the device is improved, consistency of the BVdss is improved, and EAS capability is improved.

The present invention relates to a vertically stacked micro display panel without a color filter, comprising: a back wafer having a plurality of CMOS electrode pads arranged on the upper surface thereof; and a plurality of LED stacks each including a plurality of light-emitting portions and a plurality of bonding layers stacked in a vertical direction and arranged on the plurality of CMOS electrode pads, the plurality of LED stacks each having a short channel formed in at least one of the first light-emitting portion, the second light-emitting portion, and the third light-emitting portion, the short channel being formed in the first light-emitting portion, the second light-emitting portion, and the third light-emitting portion, and the third light-emitting portion being formed in the second light-emitting portion. A current is applied to the light-emitting section in which the short channel is not formed, and only a specific color is emitted.

The invention discloses a modification preparation method of a wide-area mesophase asphalt-based silicon-carbon composite electrode material, which uses petroleum-based wide-area mesophase asphalt as a carbon source and oxygen-containing organosilicon as a silicon source. Through a hydrothermal reaction, the organosilicon is first deposited in situ on the surface of the carbon material to form a uniform coating layer, and the silicon-carbon combination is tighter; the void structure generated by calcium carbonate as a sacrificial layer reserves enough space for the expansion of silicon, and the outermost layer is coated with the wide-area mesophase asphalt again to prepare a silicon-carbon composite electrode material with a "carbon-silicon-void-carbon" quaternary structure. The petroleum-based wide-area mesophase asphalt has the characteristics of consistent arrangement and orientation of carbon layer construction units and high flatness of the carbon layer, which effectively ensures the smooth embedding and extraction of lithium ions during long-term circulation and has high cycle stability. The prepared electrode material has the advantages of good conductivity, good rate performance, and stable cycle performance.

The present invention relates to a vertically stacked micro display panel, characterized by comprising: a back surface wafer having a plurality of CMOS electrode pads arranged on the upper surface thereof; a plurality of LED stacks each including a plurality of light emitting portions and a plurality of bonding layers stacked in a vertical direction, the plurality of LED stacks being arranged on the plurality of CMOS electrode pads; and a common electrode formed on the plurality of LED stacks, each of the plurality of LED stacks forming a short-circuit channel in at least one of the plurality of light-emitting portions such that current flows to the light-emitting portion in which the short-circuit channel is not formed, thereby emitting only a specific color, the short-circuit channel having a predetermined depth and width. According to the present invention, even if a vertically stacked tandem structure is adopted, a color filter is not required, so that the chromaticity of the micro display panel can be greatly improved, and the process complexity and productivity can be greatly improved.

The invention discloses a manufacturing method of a super junction device. The manufacturing method comprises the following steps: growing a first epitaxial layer; a trench gate is formed in the active region, the gate conductive material layer outside the gate trench is removed, and the top surface of the gate conductive material layer in the gate trench is flat; forming a well region in the active region and the transition region and annealing; forming a second groove; growing a second conductive type doped second epitaxial layer in the second groove, completely removing the second epitaxial layer outside the second groove, and flattening the surface of the second epitaxial layer in the second groove; a subsequent front process is completed, and a thermal process is set according to the requirement for controlling PN impurity mutual diffusion of the super junction structure, wherein the subsequent front process comprises the step of forming a protective epoxy film covering the inner side area of a cut-off area of the transition area and the terminal area; and completing a back process. According to the invention, mutual diffusion of PN impurities of the super junction structure can be effectively controlled, and the reliability of the product can be improved.