280results about How to "Good etching" patented technology

The present invention discloses a process for depositing a carbon containing silicon oxide film, or a carbon containing silicon nitride film having enhanced etch resistance. The process comprises using a silicon containing precursor, a carbon containing precursor and a chemical modifier. The present invention also discloses a process for depositing a silicon oxide film, or silicon nitride film having enhanced etch resistance comprising using an organosilane precursor and a chemical modifier.

A method of depositing an oxide film on a template for patterning in semiconductor fabrication, includes: (i) providing a template having patterned structures thereon in a reaction space; and (ii) depositing an oxide film on the template by plasma-enhanced atomic layer deposition (PEALD) using nitrogen gas as a carrier gas and also as a dilution gas, thereby entirely covering with the oxide film an exposed top surface of the template and the patterned structures.

A method for fabricating a 3-D monolithic memory device in which a via and trench are etched using an amorphous carbon hard mask. The via extends in multiple levels of the device as a multi-level vertical interconnect. The trench extends laterally, such as to provide a word line or bit line for memory cells, or to provide other routing paths. A dual damascene process can be used in which the via is formed first and the trench is formed second, or the trench is formed first and the via is formed second. The technique is particularly suitable for deep via applications, such as for via depths of greater than 1 μm. A dielectric antireflective coating, optionally with a bottom antireflective coating, can be used to etch an amorphous carbon layer to provide the amorphous carbon hard mask.

The disclosed technology relates generally to methods and systems for controlling the release of micro devices. Prior to transferring micro devices to a destination substrate, a native substrate is formed with micro devices thereon. The micro devices can be distributed over the native substrate and spatially separated from each other by an anchor structure. The anchors are physically connected / secured to the native substrate. Tethers physically secure each micro device to one or more anchors, thereby suspending the micro device above the native substrate. In certain embodiments, single tether designs are used to control the relaxation of built-in stress in releasable structures on a substrate, such as Si (1 1 1). Single tether designs offer, among other things, the added benefit of easier break upon retrieval from native substrate in micro assembly processes. In certain embodiments, narrow tether designs are used to avoid pinning of the undercut etch front.

A method of manufacturing an MEMS sensor according to the present invention includes the steps of: forming a first sacrificial layer on one surface of a substrate; forming a lower electrode on the first sacrificial layer; forming a second sacrificial layer made of a metallic material on the first sacrificial layer to cover the lower electrode; forming an upper electrode made of a metallic material on the second sacrificial layer; forming a protective film made of a nonmetallic material on the substrate to collectively cover the first sacrificial layer, the second sacrificial layer and the upper electrode; and removing at least the second sacrificial layer by forming a through-hole in the protective film and supplying an etchant to the inner side of the protective film through the through-hole.

The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.

In a particular illustrative embodiment, a method of forming a magnetic tunnel junction (MTJ) device is disclosed that includes forming a trench in a substrate. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The method also includes planarizing the MTJ structure. In a particular example, the MTJ structure is planarized using a Chemical Mechanical Planarization (CMP) process.

The invention relates to a mask plate and a manufacture method thereof. The mask plate comprises a lightproof region, a fully transparent region and a partial transparent region; the partial transparent region is formed in a such way that a semi-transparent part and a transparent part are alternatively arranged. The invention is a new mask plate manufactured by combining a grey mask plate technique and halftone mask plate technique; the mask plate ensures that the exposure of photoresist at the lower part of the partial nonopaque region is uniform when in use, which is beneficial to forming the smooth surface of a partial maintaining region of the photoresist, thereby facilitating the TFT groove etch and improving the yield of array substrates, at the same time, the obliquity of the photoresist at the edge of the partial maintaining region of the photoresist is increased, thereby the technique can be accurately controlled in the process of forming the TFT groove.

A semiconductor device is provided, including two semiconductor nanowires superimposed one on top of the other or arranged next to one another, spaced one from the other and forming channel regions of the semiconductor device, a dielectric structure entirely filling a space between the nanowires and which is in contact with the nanowires, a gate dielectric and a gate covering a first of the nanowires, sidewalls of the nanowires and sidewalls of the dielectric structure when the nanowires are superimposed one on top of the other, or covering a part of the upper faces of the nanowires and a part of an upper face of the dielectric structure when the nanowires are arranged next to one another, and wherein the dielectric structure comprises a portion of dielectric material with a relative permittivity greater than or equal to 20.

The present disclosure relates to methods for selectively etching a porous semiconductor layer to separate a thin-film semiconductor substrate (TFSS) having planar or three-dimensional features from a corresponding semiconductor template. The method involves forming a conformal sacrificial porous semiconductor layer on a template. Next, a conformal thin film silicon substrate is formed on top of the porous silicon layer. The middle porous silicon layer is then selectively etched to separate the TFSS and semiconductor template. The disclosed advanced etching chemistries and etching methods achieve selective etching with minimal damage to the TFSS and template.

A method and apparatus for detecting the endpoint in a dry plasma etching system comprising a first electrode (e.g., upper electrode) and a second electrode (e.g., lower electrode) upon which a substrate rests is described. A direct current (DC) voltage is applied between the first electrode and a ring electrode surrounding the second electrode, and the DC current is monitored to determine the endpoint of the etching process. The DC current is affected by the impedance of the plasma, and therefore responds to many variations including, for example, the plasma density, electron / ion flux to exposed surfaces, the electron temperature, etc.

The fabrication of an integrated circuit includes a first phase of producing an electronic chip and a second phase of producing at least one auxiliary component placed above the chip and of producing a protective cover which covers the auxiliary component. The first phase of producing the chip is effected from a first semiconductor substrate and comprises the formation of a cavity lying in a chosen region of the chip and emerging at the upper surface of the chip. The second production phase includes the production of the auxiliary component from a second semiconductor substrate, separate from the first, and then the placement in the cavity of the auxiliary component supported by the second substrate and the mutual adhesion of the second substrate to the upper surface of the chip lying outside the cavity. The second substrate then also forms the protective cover.

Provided is a copper foil for a printed wiring board including a roughened layer on at least one surface thereof. In the roughened layer, the average diameter D1 at the particle bottom being apart from the bottom of each particle by 10% of the particle length is 0.2 to 1.0 μm, and the ratio L1 / D1 of the particle length L1 to the average diameter D1 at the particle bottom is 15 or less. In the copper foil for printed wiring board, when a copper foil for printed wiring having a roughened layer is laminated to a resin and then the copper layer is removed by etching, the sum of areas of holes accounting for the resin roughened surface having unevenness is 20% or more. The present invention involves the development of a copper foil for a semiconductor package substrate that can avoid circuit erosion without causing deterioration in other properties of the copper foil. In particular, an object of the present invention is to provide a copper foil for a printed wiring board and a method of producing the copper foil, in which the adhesion strength between the copper foil and the resin can be enhanced by improvement of the roughened layer of the copper foil.

The present invention relates to a Multiple Gate Field Effect Transistor structure and a method for fabricating same. The Multiple Gate Field Effect Transistor structure includes a fin structure made from at least one active semiconductor layer of a silicon on insulator (SOI) structure on a buried insulator of the structure. The Multiple Gate Field Effect Transistor structure also includes an insulator of at least one high-k layer of a material having a dielectric constant that is higher than silicon oxide. This has the advantage that the high-k layer acts as a better etch stop than silicon oxide during formation and cleaning of the fin resulting in a lower recess and undercut effect on the socket of the fin. This leads to a higher stability of the formed fin and enables a smooth finishing of the fin by etching and cleaning steps.

An aqueous one-pack self-etching and self-priming dental adhesive composition having a pH of at most 2, which comprises: (i) a polymerizable N-substituted alkylacrylic or acrylic acid amide monomer which optionally contains an inorganic acidic moiety selected from a phosphonic acid moiety or a sulfonic acid moiety, and (ii) a curing system.

Disclosed is equipment for measuring a silicon concentration in a phosphoric acid solution under use as an etching solution during operation of a semiconductor substrate processing system. The equipment is provided with at least a reaction tank and a concentration-measuring tank. The reaction tank includes a reaction unit for adding hydrofluoric acid to a predetermined constant amount of the phosphoric acid solution drawn out of the semiconductor substrate processing system to form a silicon fluoride compound and then causing the silicon fluoride compound to evaporate. The concentration-measuring tank comprises a hydrolysis unit for bubbling the silicon fluoride compound, which has evaporated from the reaction tank, through deionized water to hydrolyze the silicon fluoride compound and a measurement unit for determining a change rate of silicon concentration in the deionized water subsequent to the bubbling. Also disclosed is a method for measuring a silicon concentration in a phosphoric acid solution under recirculation and use as an etching solution in a semiconductor substrate processing system in operation.

A plasma etching method and apparatus. In the plasma etching apparatus, pluralities of RF power supplies are respectively connected to upper and lower electrode via relevant matching networks to enable generation of various ion densities and ion energies of plasma by individually changing RF powers applied to the upper and lower electrodes through control of the RF power supplies, so that the plasma etching apparatus can perform all processes which includes a process requiring a low ion density and a low ion energy, a process requiring the low ion density and a high ion energy, a process requiring a high ion density and the low ion energy, and a process requiring the high ion density and the high ion energy, thereby realizing various plasma etching processes.

The invention relates to a frosting liquid, a preparation method and uses thereof, and an anti-glare glass preparation method, and provides a frosting liquid, which is prepared by mixing the followingraw materials by weight: 10-17 parts of ammonium fluoride, 7-12 parts of sulfuric acid, 3-5 parts of calcium fluoride, 3-5 parts of ammonium sulfate, 15-20 parts of potassium sulfate, and 130-140 parts of water. The invention further provides the an anti-glare glass preparation method, which comprises: (1) placing a glass in a frosting liquid; and (2) introducing a gas into the frosting liquid, and carry out a reaction. According to the present invention, the anti-glare glass prepared by using the frosting liquid through the preparation method has advantages of high light transmittance, highgloss, fine surface particles, uniform particle distribution and the like.

A method of manufacturing an MEMS sensor according to the present invention includes the steps of: forming a first sacrificial layer on one surface of a substrate; forming a lower electrode on the first sacrificial layer; forming a second sacrificial layer made of a metallic material on the first sacrificial layer to cover the lower electrode; forming an upper electrode made of a metallic material on the second sacrificial layer; forming a protective film made of a nonmetallic material on the substrate to collectively cover the first sacrificial layer, the second sacrificial layer and the upper electrode; and removing at least the second sacrificial layer by forming a through-hole in the protective film and supplying an etchant to the inner side of the protective film through the through-hole.

The present invention discloses an environmental protection ashing treatment process of calendaring copper foil. The environmental protection ashing treatment process comprises degreasing washing, roughening electroplating, curing electroplating, nickel alloy electroplating, zinc electroplating, chromate passivation treatment, silane treatment and the like. According to the present invention, after electrochemical degreasing, roughening and curing treatment (roughening and curing can be selected more than two times according to the requirement) Cu grain electrodeposition are performed on the calendaring copper foil, the nano-scale nickel alloy is electrodeposited under the acidic condition, the thin metal zinc layer is electroplated, and finally the chromate passivation treatment is performed and the silane coupling agent is uniformly sprayed on the surface; As, Sb, Cd and other toxic and harmful metals are not added, and the alloy system electrodeposition and other relatively simple processes are used to treat the process; and under the optimization of the process parameters, the environmentally friendly surface treated copper foil with characteristics of good performance, meeting of FPC production requirements, gray appearance of gray, no toxicity and no harm can be obtained.

A method for manufacturing a semiconductor device, includes: (a) forming a SiGe layer on a Si substrate; (b) forming a Si layer on the SiGe layer; (c) forming a dummy pattern made of SiGe in a dummy region of the Si substrate; and (d) wet-etching and removing the SiGe layer formed under the Si layer. In the step (d), an etchant is kept to contact the dummy pattern from before a complete remove of the SiGe layer to an end of the etching.

Disclosed is a method for fabricating a transistor of a memory device capable of preventing voids from being created when forming a low-resistant gate electrode. The method includes the steps of forming an active area by etching a semiconductor substrate, forming a field oxide layer in the semiconductor substrate and forming a recess by etching the field oxide layer. A gate insulation layer is formed along an upper surface of the active area and an exposed portion of the active area. A gate electrode is formed on the field oxide layer such that the gate electrode extends across an upper portion of the active area while being overlapped with a channel area and the recess. The first conductive layer to be patterned has the same thickness, so the low-resistant gate electrode is easily fabricated without forming the voids.

A shadow mask blank of Fe-Ni alloy which exhibits excellent uniformity of diameter of apertures formed by perforation with etching for the passage of electron beams, consisting of 34-38% Ni, 0.05-0.5% Mn, 4-20 ppm S, and the balance Fe and no more than specified limits of C, Si, Al, and P, with MnS inclusions 50-1,000 nm in diameter dispersed at the density of at least 1,500 / mm2 or simply with etched holes 0.5-10 mum in diameter emerging at the density of at least 2,000 / mm2 when the blank is immersed in a 3% nitric acid-ethyl alcohol solution at 20° C. for 30 seconds. A method of manufacturing the blank comprises hot rolling of a slab of the Fe-Ni alloy, cooling, recrystallization annealing, cold rolling, etc. under controlled conditions: e.g., hot rolling the slab at 950-1,250° C. to 2-6 mm thick, cooling the stock in the range of 900-700° C. at the rate of 0.5° C. / second, continuously passing the stock through a heating furnace at 850-1,100° C. for recrystallization annealing to adjust the mean diameter of the recrystallized grains to 5-30 mum, and performing the cold rolling before the final recrystallization annealing at a reduction ratio of 50-85% and the final cold rolling at a reduction ratio of 10-40%.

The invention discloses a developable UV cured hydrofluoric acid-resistant protection glue, which comprises the following components by mass percentage: 15-75% of main resin, 10-55% of auxiliary resin and 6-30% of active monomer. The developable UV cured hydrofluoric acid-resistant protection glue has excellent gluing capability by comparing with the hydrofluoric acid-resistant protection glue in prior art, and has extremely high bonding intensity and excellent hydrofluoric acid-resistant etching performance.

The present invention provides an etchant, capable of preventing dimensional precision of a wiring pattern from reducing when removing a chemical copper plate in a half addition process. A first etchant of the invention is characterized in that it is a copper etchant containing sulphuric acid, hydogen peroxide and water, and containing more than two benzotriazole derivates containing at least oneof carboxyl and dydroxyl in a molecule. A second etchant of the invention is characterized in that it is a copper etchant containing sulphuric acid, hydogen peroxide and water, and containing pyrrolehaving heteroatom of nitrogen atom only in a loop, and polyprotic acid having more than two carboxyl or salts thereof.