ROM (Read Only Memory), data reading method thereof and electronic equipment

Abstract

The invention relates to the technical field of memories, and particularly provides an ROM (Read Only Memory), a data reading method thereof and electronic equipment, and the ROM comprises a storage circuit, a reference circuit and a comparison circuit, the storage circuit comprises a multiplexer and a storage array; the reference load of the reference circuit is larger than the minimum load and smaller than the maximum load of the read bit line, the voltage-time change slope of the reference voltage generated during reading is smaller than the slope when the memory unit reads 0 and larger than the slope when the memory unit reads 1, and the read bit line is a bit line corresponding to the multiplexer; the comparison circuit compares a reference voltage with a read voltage to determine to output a read digital signal, and the read voltage is an output voltage of a read memory cell. The problem that a large-capacity ROM read-only memory is low in reading speed and prone to misreading due to the fact that the load is high in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of memory, and in particular to a ROM memory, a data reading method thereof, and an electronic device. Background Art

[0002] In the related art, ROM memory includes: a multiplexer circuit, a storage matrix, an inverter, such as Figure 1 As shown in the figure, the multiplexer circuit can select one BL (bit line) column to enable, and the WL (word line) can select one row to enable, thereby locking a specific memory cell in the memory matrix. The memory matrix includes multiple memory cells arranged in an array, which are composed of field-effect transistors. These transistors can be programmed to determine whether the gate is connected to the word line and whether the source or drain is connected to the bit line. If the transistor source or drain is programmed to be grounded, a 0 is stored. In the other case, if the transistor source or drain is not programmed to be grounded, a 1 is stored. The inverter flip voltage is a fixed threshold. When the GBL output voltage reaches the inverter flip voltage, it passes through two stages of inverters and outputs the corresponding signal.

[0003] However, the ROM has a large memory capacity and a heavy load on the BL, resulting in a large slope of the voltage signal at the input of the inverter, a slow change in the voltage input to the inverter, and a slow reading speed of the inverter. The leakage of the MOS tube in a small-size process is more obvious, which may cause the GBL to leak to a low level when reading 1, causing the inverter to flip, thereby reading an incorrect value.

[0004] Currently, no effective solution has been proposed to the problem that the ROM read-only memory in the related art has a large capacity and a high load, which results in a slow voltage change of the input inverter, a slow reading speed of the inverter, and is prone to reading errors. Summary of the Invention

[0005] The present invention provides a ROM memory and a data reading method and an electronic device thereof, which at least solve the problem in the related art that the ROM read-only memory has a large capacity and a high load, resulting in a slow voltage change of the input inverter, a slow reading speed of the inverter, and easy reading errors.

[0006] According to one aspect of the present invention, a ROM memory is provided, comprising: a storage circuit, a reference circuit, and a comparison circuit; the storage circuit comprises a multiplexer and a storage array, the storage array comprising a plurality of storage cells arranged in an array; the reference circuit is used to generate a reference voltage based on a reference load during reading, wherein the reference load is greater than the minimum load of any read bit line and less than the maximum load of any read bit line, so that the voltage-time variation slope of the reference voltage is less than the voltage-time variation slope when the storage cell reads 0 and greater than the voltage-time variation slope when the storage cell reads 1, wherein the read bit line is the bit line corresponding to the multiplexer during reading; the two input terminals of the comparison circuit are respectively connected to the reference circuit and the storage circuit, for comparing the reference voltage and the read voltage to determine the corresponding output read digital signal, wherein the read voltage is the output voltage of the storage circuit when reading data stored in the storage cell.

[0007] As an optional solution, the reference circuit includes the same number of first MOS transistors on the read bit line and a preset number of storage cells as reference cells; one end of the source or drain of the reference cell is connected to the bit line and the other end is grounded, so that all reference cells store 0; the enable signal of the gate of a storage cell in the reference cell is the corresponding virtual bit line, so that when any corresponding bit line in the storage array is turned on, the virtual bit line is also turned on; the gates of the remaining storage cells in the reference cell are all set to a low level to ensure that the NMOS is in a closed state.

[0008] As an optional solution, the preset number is greater than the number of storage units in the bit line, and the preset number is twice the number of storage units in the bit line.

[0009] As an optional solution, the reference circuit includes the same number of first MOS transistors on the read bit line and the same number of storage cells as reference cells; the enable signal of the gate of a storage cell in the reference cell is the corresponding virtual bit line, so that any corresponding bit line in the storage array is turned on, the virtual bit lines are all turned on, and one end of the source or drain of the storage cell is connected to the bit line and the other end is grounded, so that the reference cell stores 0; the source or drain of the other storage cells in the reference cell are all connected to the bit line, so that the reference cell stores 1, and the gates are all set to a low level to ensure that the NMOS is in a closed state.

[0010] As an optional solution, it further includes a pre-charging device, which is connected to both the reference circuit and the storage circuit; there are two pre-charging devices, which are respectively connected to the reference circuit and the storage circuit.

[0011] As an optional solution, the comparison circuit includes two second MOS transistors; the gates of the two second MOS transistors are respectively connected to the reference circuit and the storage circuit, the sources of the second MOS transistors are connected, the drains of the second MOS transistors are connected to the first NMOS transistor, and the drain output end of the first MOS transistor is used to output a digital signal.

[0012] As an optional solution, the comparison circuit also includes two first PMOS tubes and two first NMOS tubes; the gate of the first PMOS tube is connected to the drain of another first PMOS tube, and the drain of the first PMOS tube is connected to the drain of the corresponding first NMOS tube; the gate of the first NMOS tube is connected to the drain of another first NMOS tube, and the source of the first NMOS tube is connected to the corresponding second MOS tube; and each drain of the first PMOS tube and the first NMOS tube is provided with an independent pull-up circuit.

[0013] As an optional solution, the pre-charging device is a second PMOS tube; the gate of the second PMOS tube is connected to the enable pre-charging signal, the source of the second PMOS tube is connected to the high voltage end, and the drain of the second PMOS tube is connected to the pre-charging circuit.

[0014] As an optional solution, the comparison circuit is a sense amplifier.

[0015] According to another aspect of the present invention, a data reading method for a ROM memory is provided, comprising: selecting a memory cell to be read and a reading voltage of a bit line thereof based on a multiplexer of a memory circuit, wherein the memory circuit comprises a multiplexer and a memory array, and the memory array comprises a plurality of memory cells arranged in an array; obtaining a reference voltage from a reference circuit, wherein the reference circuit is configured to generate a reference voltage based on a reference load, wherein the reference load is greater than a minimum load of any read bit line and less than a maximum load of any read bit line, so that a voltage-time variation slope of the reference voltage is less than a voltage-time variation slope when the memory cell reads 0 and greater than a voltage-time variation slope when the memory cell reads 1, wherein the read bit line is a bit line corresponding to the multiplexer during reading; inputting the reference voltage and the read voltage into a comparison circuit, and the comparison circuit outputs a corresponding read digital signal, wherein two input terminals of the comparison circuit are respectively connected to the reference circuit and the memory circuit.

[0016] As an optional solution, before a multiplexer based on a storage circuit selects a storage cell to be read and reads the voltage of the bit line thereof, the method further includes: independently precharging the reference circuit and the storage circuit through two independent precharging devices, wherein two precharging devices are provided and are connected to the reference circuit and the storage circuit respectively.

[0017] According to another aspect of the present invention, an electronic device is provided, comprising any one of the above-mentioned ROM memories.

[0018] The ROM memory provided by the embodiment of the present invention adopts a comparison circuit and a reference circuit. When reading data, the reference circuit can generate a voltage change signal with a slope between the storage cell reading 0 and the storage cell reading 1. When reading data, the output data signal can be quickly determined based on the magnitude of the reference voltage and the read voltage, thereby avoiding the problem of reading errors caused by the read voltage decaying to the flip threshold of the inverter when reading 1 when the reading time is long. This solves the problem in the related art that the ROM memory has a high load, the input end slope of the inverter is large, and the voltage change of the input inverter is slow, resulting in slow reading speed and easy reading errors. The technical effect of faster data reading after comparing the reference voltage and the read voltage and avoiding reading errors is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without inventive effort.

[0020] Figure 1 It is a schematic diagram of the ROM memory structure of the prior art.

[0021] Figure 2 It is a schematic diagram of the ROM memory structure of an embodiment of the present invention.

[0022] Figure 3-1 This is a schematic diagram of a reference circuit structure of a ROM memory according to an embodiment of the present invention.

[0023] Figure 3-2 This is a schematic diagram of another reference circuit structure of a ROM memory according to an embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram of the GBL and RBL voltage states in the ROM memory created by the present invention.

[0025] Figure 5 It is a flow chart of the ROM memory implementation process of the embodiment created by the present invention.

[0026] Figure 6 It is a flow chart of the specific implementation process of the ROM memory of the embodiment created by the present invention.

[0027] The figure numbers of the above drawings are as follows: 100, storage array; 100*, storage matrix; 200, multiplexer; 200*, multiplexer circuit; 300, sense amplifier; 400, reference circuit; 500, pre-charge device. DETAILED DESCRIPTION

[0028] The following describes embodiments of the present invention in more detail with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0029] like Figure 1 As shown, a conventional ROM (Read-Only Memory) memory includes: a precharge device, a multiplexer circuit 200*, a storage matrix 100*, and an inverter.

[0030] The precharge device pulls the precharge enable to a low level to turn on the PMOS (P-channel Metal-Oxide-Semiconductor Field-Effect Transistor) for precharging. After pulling the bit line to the VDD (drain voltage) voltage, the precharge enable is pulled high to turn off the PMOS.

[0031] The multiplexer 200 can select to open one of the columns of BL (bit lines), and the WL (word line) can select to open one of the rows, thereby locking a certain memory cell in the memory matrix 100*.

[0032] Memory matrix 100* includes a plurality of memory cells arranged in an array. These cells are composed of field-effect transistors. These transistors can be programmed to determine whether their gates are connected to word lines (WL) and their sources or drains are connected to bit lines (BL). If the transistor source or drain is programmed to be grounded, a 0 is stored; if it is programmed to be ungrounded, a 1 is stored. If the GBL (Global Bit Line) outputs a 0, it will pass through two stages of inverters and output a 0. If it outputs a 1, because the BL is high after precharging, the BL remains at that high level and passes through two stages of inverters to output a 1.

[0033] Therefore, the time it takes to read a 0 depends on the speed of the inverter. Since ROM memory capacity is typically large, the load on the BL is also heavy, resulting in a large slope at the inverter input. This slows down the voltage change at the input to the inverter, slowing the inverter read speed. Leakage in MOS (metal-oxide-semiconductor) transistors is more pronounced on small-scale processes. This can cause the GBL to leak low when reading a 1, causing the inverter to flip, resulting in an incorrect read value.

[0034] In order to improve the ROM reading speed and avoid reading errors, the embodiments of the present invention provide a ROM memory and a data reading method thereof, and an electronic device, such as Figure 2 As shown, it includes: a storage circuit, a reference circuit 400, and a comparison circuit; the storage circuit includes a multiplexer 200 and a storage array 100, and the storage array 100 includes a plurality of storage cells arranged in an array; the reference circuit 400 is used to generate a reference voltage based on a reference load when reading, and the reference load is greater than the minimum load of any read bit line and less than the maximum load of any read bit line, so that the voltage-time change slope of the reference voltage is less than the voltage-time change slope when the storage cell reads 0, and greater than the voltage-time change slope when the storage cell reads 1, wherein the read bit line is the bit line corresponding to the multiplexer 200 when reading; the two input terminals of the comparison circuit are respectively connected to the reference circuit 400 and the storage circuit, and are used to compare the reference voltage and the read voltage to determine the corresponding output read digital signal, wherein the read voltage is the output voltage of the storage circuit when reading the data stored in the storage cell.

[0035] Among them, the memory circuit provided by the embodiment of the present invention is as follows: Figure 2 As shown, multiplexer 200 and memory array 100 are included. Multiplexer 200 is composed of multiple NMOS transistors arranged in rows, including N21, N22, and N23. The gates of these NMOS transistors are used for SEL (selection function) to select and enable one column of bit lines. The drains are connected to GBLs, and the sources are connected to each bit line. Memory array 100 includes multiple memory cells arranged in an array, including NMOS transistors N11, N12, N13, N14, N15, N16, N17, N18, and N19. These NMOS transistors can be programmed to determine whether the gate is connected to the word line and whether the source or drain is connected to the bit line. If the source or drain of the transistor is programmed to be grounded, it stores 0. If the source or drain of the transistor is programmed to be not grounded, it stores 1.

[0036] The first MOS transistor can be a PMOS transistor or an NMOS transistor. In this embodiment, an NMOS transistor is used as the first MOS transistor, which has advantages over a PMOS transistor such as faster switching speed, higher energy efficiency, and higher integration.

[0037] Among them, the reference circuit 400 provided by the embodiment of the present invention is as follows: Figure 2 As shown, the drain of N41 in the reference circuit 400 is connected to the drain of P51 in the precharge device, and the drain of N41 in the reference circuit 400 is connected to the gate of N32 in the comparison circuit.

[0038] In the related art, the solution of using inverters for reading is that the read data structure is limited by the inverter flip point and flip time, which increases the read time and has significant leakage. It may cause the GBL to leak to a low level when reading 1, causing the inverter to flip, thereby reading an erroneous value of 0. Figure 4 As shown, the RBL (Read Bit-Line) black line represents the reference voltage change, the GBL red line represents the voltage change when the memory cell reads 0, and the GBL blue line represents the voltage change when the memory cell reads 1; when reading data, the reference circuit 400 can generate a voltage change signal whose slope is always between the memory cell reading 0 and the memory cell reading 1. When reading data, the output data signal can be quickly determined based on the size of the reference voltage and the memory cell read voltage, avoiding the read error problem caused by the read voltage when reading 1 decaying to the flip threshold of the inverter when the reading time is long.

[0039] The comparator circuit has two input terminals, connected to the drain of N41 of the reference circuit 400 and the drain of N23 of the storage circuit, respectively. Comparator circuits compare two voltages and can be analog, digital, or mixed-signal. This example uses a digital comparator circuit, which offers advantages such as low cost, flexibility, and seamless integration with digital systems.

[0040] The ROM memory provided in this embodiment employs a comparison circuit and a reference circuit 400. When reading data, the reference circuit 400 can generate a voltage change signal with a slope between that of a memory cell reading 0 and that of a memory cell reading 1. When reading data, the output data signal can be quickly determined based on the magnitude of the reference voltage and the read voltage, thereby avoiding the problem of misreading caused by the read voltage decaying to the inverter's flip threshold when reading 1 when the read time is long. This solves the problem in the related art that the ROM memory has a high load, the input slope of the inverter is large, and the voltage change of the input inverter is slow, resulting in slow reading speed and easy misreading. This achieves the technical effect of faster data reading after comparing the reference voltage and the read voltage, thus avoiding misreading.

[0041] As an optional solution, the reference circuit 400 includes the same number of first MOS transistors N41 on the read bit lines, and a preset number of memory cells N42 and N43 as reference cells; one end of the source or drain of the reference cells N42 and N43 is connected to the bit line, and the other end is grounded, so that all reference cells store 0; the enable signal of the gate of a memory cell N42 in the reference unit is the corresponding virtual bit line, so that any corresponding bit line in the memory array 100 is turned on, and the virtual bit line is turned on; the gates of the remaining memory cells N43 in the reference unit are all set to a low level to ensure that the memory cells are in a closed state.

[0042] Designing the same number of first MOS transistors can fully match the PVT (PVT is the abbreviation of three key environmental parameters, representing process, voltage, and temperature) sensitive parameters of the two, offsetting the impact of external environmental changes and ensuring consistent attenuation characteristics of the reference signal and bit line signal.

[0043] The reference cells are preset to store 0 to provide a reference voltage that represents 0. The preset number matches the number of memory cells on the bit line, simulating the actual bit line load. This ensures that the reference voltage accurately reflects the actual bit line voltage in the 0 state, avoiding comparison errors caused by load differences.

[0044] The purpose of the dummy bit line design is to synchronize the activation of any word line corresponding to a bit line in memory array 100, turning on the dummy bit line, thereby turning on the corresponding MOS transistor N42 in the reference cell and putting reference circuit 400 into operation. This synchronization ensures that the reference signal and the bit line signal are time-aligned, preventing misreading caused by an early or late reference signal.

[0045] TIE0 permanently connects the gate of transistor N43 to a logic low, forcing it to be cut off or maintain a fixed state. Except for the selected memory cell, the select transistors of all unselected cells on the bit line are all off. However, these cells still affect the speed of the bit line voltage change through their off select transistors. This simulates the load on the unselected bit line, ensuring that the load on the reference bit line exactly matches the actual bit line.

[0046] As an optional solution, the preset number is greater than the number of memory cells in the bit line, and the preset number is twice the number of memory cells in the bit line.

[0047] Among them, the reference circuit 400 provided by the embodiment of the present invention is as follows: Figure 3-1As shown in the figure, if the number of reference cells is equal to the number of memory cells on the bit line (assuming N), and all of them store 0s, the reference voltage is essentially the reference voltage after the N cells storing 0s pull down. In this case, the pull-down capability of the 2N cells storing 0s is too close, resulting in insufficient margin for distinguishing between 0 and 1, especially in low-voltage scenarios. The pull-down capability of the 2N cells storing 0s is twice that of the N cells. When connected in parallel, the total pull-down current is greater, which will pull the voltage of the reference bit line lower than that of the N cells storing 0s. This lower reference voltage creates a larger voltage difference with the read voltage of the bit line in the 1 state, while maintaining a reasonable distance from the 0 state. This makes the comparator's read bit line voltage more balanced with the reference voltage, reducing false positives caused by voltage proximity.

[0048] The pull-down capability of a single memory cell can experience random process variations, leading to unstable voltage characteristics. When the number of reference cells is small, this random variation directly impacts the stability of the reference voltage. However, using 2N reference cells, the characteristics of multiple cells are statistically averaged to offset random variations, minimizing the impact of a single cell anomaly on the overall reference voltage.

[0049] In high-density memory, bit lines can be slightly pulled down by other cells due to adjacent channel interference, effectively increasing the load. Setting the number of reference cells to 2N better adapts to the actual bit line load and ensures read reliability in complex scenarios.

[0050] As an optional solution, referring to circuit 400, as shown in FIG. Figure 3-2 As shown, it includes the same number of first MOS transistors N41* on the read bit line, and the same number of memory cells, including N42* and N43* as reference cells; the enable signal of the gate of a memory cell N42* in the reference cell is the corresponding virtual bit line, so that any corresponding bit line in the memory array 100 is turned on, and the virtual bit lines are all turned on, and the source or drain of other reference cells, such as N43*, is connected to the bit line at one end and grounded at the other end, so that the reference cell stores 0; the source or drain of other memory cells in the reference cell are all connected to the bit line, so that the reference cell stores 1, and the gates are all set to a low level to ensure that the memory cell is in a closed state.

[0051] The design of partially storing 0s and partially storing 1s is to make the reference voltage closer to the bit line voltage characteristics of random data in the actual memory array 100, avoiding misjudgment caused by extreme data distribution (such as all 0s or all 1s). The reference cell simulates the averaging effect of this random distribution by mixing cells storing 0s and cells storing 1s, so that the reference voltage is exactly halfway between the all-0 bit line voltage and the all-1 bit line voltage.

[0052] The reference cell storing 0 is hard-wired to ground at one end, ensuring its stable state of 0. The reference cell storing 1 has its gate connected to TIE0, keeping it always on and stably storing 1. This design prevents fluctuations in the reference cell's state due to noise, charge leakage, and other issues, ensuring stable reference voltage output. If the reference cell state is unstable, the reference voltage will fluctuate dramatically, directly leading to read errors.

[0053] If neither the source nor the drain of the reference cell MOS transistor is connected to the bit line, or both are connected to the bit line, the reading is 1, which can be controlled according to programming. In this example, the preferred method is to ground both the source or drain of the MOS transistor to store a 1 in the reference cell. Connecting both the source and drain to the bit line allows the 1 state of the reference cell and the 1 state of the actual storage cell to share the same electrical environment, synchronize dynamic response, and share PVT changes, thus ensuring highly consistent characteristics between the two, achieving a stable reference voltage and allowing the read circuit to accurately interpret the read signal.

[0054] As an optional solution, a pre-charging device 500 is further included, and the pre-charging device 500 is connected to both the reference circuit 400 and the storage circuit; two pre-charging devices 500 are provided, and the two pre-charging devices 500 are respectively connected to the reference circuit 400 and the storage circuit.

[0055] like Figure 2 As shown, the drain of P51 in the pre-charge device 500 is connected to the reference bit line RBL in the reference circuit 400, and the drain of P52 in the pre-charge device 500 is connected to the global bit line GBL in the storage circuit.

[0056] The precharge device 500 precharges the bit lines of the storage circuit and the reference circuit 400, sets the PREEN signal to a low level to turn on P51 and P52 for precharging, and pulls the GBL and RBL levels up to VDD.

[0057] The storage circuit is connected to the precharge device 500 to quickly charge the bit line to a high position in preparation for reading the 0 state; the reference circuit 400 is connected to the precharge device 500 to charge the reference bit line to VDD, which needs to be stable and accurate.

[0058] Sharing a single pre-charging device 500 can lead to inconsistent charging times due to load variations, and the charge and discharge noise from the storage circuit can interfere with the stability of the reference voltage. Providing two pre-charging devices 500 and independent pre-charging ensures that the timing of each device is independent of the other, allowing the charging current or timing to be adjusted based on individual needs.

[0059] Precharging the memory circuit typically consumes high power, while reference circuit 400 only needs to maintain a stable, low current. In standby mode, only precharging the reference circuit 400 can be activated to maintain a stable reference voltage, while precharging the memory circuit can be paused, further reducing power consumption. This independent power supply avoids overdesigning the reference circuit 400's power supply to meet memory precharging requirements, thereby reducing overall power consumption.

[0060] As an alternative, a comparison circuit such as Figure 2 As shown, two second MOS transistors N32 and N33 are included; the gates of the two second MOS transistors N32 and N33 are respectively connected to the RBL of the reference circuit 400 and the GBL of the storage circuit, the sources of the second MOS transistors N32 and N33 are connected, the drains of the second MOS transistors N32 and N33 are connected to the first NMOS transistors N34 and N35, and the drain output terminals of the first NMOS transistors N34 and N35 are used to output digital signals.

[0061] The output terminal is also equipped with an inverter. The gate of NMOS transistor N31 is connected to the enable precharge signal, the drain of N31 is connected to the sources of the second MOS transistors N32 and N33, and the source of N31 is grounded. N31 is turned on by the NMOS transistor low level, quickly discharging the input circuit.

[0062] When reading from memory, the voltage difference between the bit lines of the memory cell and the reference cell is typically very small, making direct identification prone to errors. The two first PMOS transistors P38 and P39 and the two first NMOS transistors N34 and N35 form a positive feedback mechanism, gradually amplifying the initial small voltage difference and ultimately stabilizing it quickly to a clear level. This circuit quickly amplifies the tiny voltage difference to a digital level, achieving high sensitivity. This structure ensures accurate distinction between the 0 and 1 states and prevents misreading.

[0063] The second MOS transistors N32 and N33 directly convert the bit line voltage difference into a current difference, reducing the intermediate conversion link; the two first PMOS transistors P38 and P39 and the two first NMOS transistors N34 and N35 directly drive the subsequent circuits, further shortening the delay and achieving the effect of improving the memory reading speed.

[0064] As an optional solution, the comparison circuit further includes two first PMOS transistors P38 and P39 and two first NMOS transistors N34 and N35; the gate of the first PMOS transistor P38 is connected to the drain of another first PMOS transistor P39, and the drain of the first PMOS transistor P38 is connected to the drain of the corresponding first NMOS transistor N34; the gate of the first NMOS transistor N34 is connected to the drain of another first NMOS transistor N35, and the source of the first NMOS transistor N34 is connected to the corresponding second MOS transistor N32; and each of the drains of the first PMOS transistors P38 and P39 and the first NMOS transistors N34 and N35 is provided with an independent pull-up circuit.

[0065] Among them, the structure provided by the embodiment of the present invention is as follows: Figure 2 As shown, the gate of P38 is connected to the drain of P39, and the drain of P38 is connected to the drain of N34; the gate of P39 is connected to the drain of P38, and the drain of P39 is connected to the drain of N35; the gate of N34 is connected to the drain of N35, and the source of N34 is connected to the drain of the corresponding second MOS transistor N32; the gate of N35 is connected to the drain of N34, and the source of N35 is connected to the drain of the corresponding second MOS transistor N33.

[0066] P36 and P37 pull up the A and C nodes of the P38 and P34 drains, respectively. The P36 and P37 drains are connected to the P38 and P34 drains, respectively. P40 and P41 pull up the B and D nodes of the P39 and P35 drains, respectively. The P40 and P41 drains are connected to the P39 and P35 drains, respectively. The sources of P36, P40, P37, and P41 are connected to the positive power supply. The gates of the PMOS transistors P36, P40, P37, and P41 in the pull-up circuit are all controlled by the enable signal.

[0067] The symmetrical design of the structures of the two first PMOS transistors P38 and P39 and the two first NMOS transistors N34 and N35 allows the effects of process deviations on both sides to offset each other, further improving stability.

[0068] The independent pull-up circuit can pull the input node up to a preset voltage, allowing the circuit to operate in the most sensitive area, maximizing the response capability to tiny input voltage differences, and achieving the effect of accurately controlling the comparison bias point.

[0069] The gates of the second MOS transistors N32 and N33 hardly absorb current, thereby avoiding interference with the voltage of the read bit line, ensuring that the real state of the memory cell is detected, and achieving accurate reading.

[0070] The drains of the second MOS transistors N32 and N33 are only connected to the gates of N34 and N35, which reduces the load on the bit line and increases the charging and discharging speed of the bit line, thereby achieving the effect of increasing the ROM reading speed.

[0071] As an optional solution, the pre-charging device 500 is a second PMOS tube P51, P52; the gate of the second PMOS tube P51, P52 is connected to the enable pre-charging signal, the source of the second PMOS tube P51, P52 is connected to the high voltage end, and the drain of the second PMOS tube P51, P52 is connected to the pre-charging circuit.

[0072] Among them, the pre-filling device 500 provided by the embodiment of the present invention is as follows: Figure 2 As shown, the gate of the second PMOS transistor P51 is connected to the enable precharge signal, the source of P51 is connected to the high voltage terminal, the drain of P51 is connected to the RBL of the reference circuit 400, and the drain of P52 is connected to the GBL of the storage circuit.

[0073] PMOS transistors are typically used to pull the precharged node to VDD, while NMOS transistors are suitable for quickly pulling the node to GND. In the precharge device 500, the precharge device uses a PMOS transistor to precharge the memory bit line to VDD, and then discharges it through the storage unit to determine whether it is 0 or 1. The PMOS transistor is used in the comparison circuit to pull the level high to establish a reference voltage.

[0074] As an optional solution, the comparison circuit is a sense amplifier.

[0075] The sense amplifier can be a voltage-type sense amplifier or a current-type sense amplifier. This embodiment uses a voltage-type sense amplifier. A sense amplifier is a circuit that quickly amplifies the weak voltage difference output by a memory cell to a standard logic level, thereby accurately reading data. It provides relatively sensitive and accurate voltage comparison capabilities and can be directly used in ROMs, eliminating the need to modify the ROM design circuit, resulting in low modification costs.

[0076] When a memory cell is read, the signal output through the bit line is often very weak. This weak signal cannot be directly recognized by subsequent circuits and is easily affected by noise during transmission. A sense amplifier can quickly detect tiny voltage differences on the bit line and efficiently amplify them to standard logic levels. This accelerates the discharge and charging of the bit line, shortens the read cycle, and improves the memory read speed.

[0077] like Figure 5 As shown, according to another aspect of the present invention, a method for reading data from a ROM memory is also provided, comprising: step S101, selecting a memory cell to be read and a read voltage of a bit line thereof based on a multiplexer 200 of a memory circuit, wherein the memory circuit comprises the multiplexer 200 and a memory array 100, and the memory array 100 comprises a plurality of memory cells arranged in an array.

[0078] Step S102: obtaining a reference voltage based on the reference circuit 400, wherein the reference circuit 400 is configured to generate a reference voltage based on a reference load, wherein the reference load is greater than a minimum load of any read bit line and less than a maximum load of any read bit line, so that a voltage-time variation slope of the reference voltage is less than a voltage-time variation slope when the memory cell reads 0 and greater than a voltage-time variation slope when the memory cell reads 1, wherein the read bit line is a bit line corresponding to the memory circuit during reading.

[0079] In step S103 , the reference voltage and the read voltage are input into a comparison circuit, and the comparison circuit outputs a corresponding read digital signal, wherein two input terminals of the comparison circuit are connected to the reference circuit and the storage circuit respectively.

[0080] The data reading method of the ROM memory provided in this embodiment uses a comparison circuit to compare a reference voltage and a read voltage. Since the slope of the voltage change signal of the reference circuit is between the slope of the memory cell reading 0 and the slope of the memory cell reading 1, when reading data, the output data signal can be quickly determined based on the magnitude of the reference voltage and the read voltage, thereby avoiding the problem of misreading caused by the read voltage decaying to the flip threshold of the inverter when reading 1 when the reading time is long. This solves the problem in the related art that the ROM memory has a high load, the input end slope of the inverter is large, and the voltage change of the input inverter is slow, resulting in slow reading speed and easy misreading. The technical effect of faster data reading after comparing the reference voltage and the read voltage and avoiding misreading is achieved.

[0081] The embodiment of the present invention also provides a specific process for reading ROM memory data, such as Figure 6 As shown, data reading begins by first selecting a row and column of memory array 100 based on the address. One of the multiplexers 200 is enabled based on the address line. By turning on SEL0, the corresponding bit line BL0 is enabled. Simultaneously, SEL of reference circuit 400 is also enabled, thereby turning on reference circuit 400. Since the source and drain of N11 in memory array 100 are connected to BL0 and VSS, respectively, the data to be read is 0. In this embodiment, the process of turning on N11 and N21 is described as follows.

[0082] Precharge the memory bit line and reference line, set the PREEN signal to a low level to turn on P51 and P52 for precharging, pull the GBL and RBL levels to VDD, and pull nodes A, B, C, and D to a high level.

[0083] Precharge is disabled and the word line is enabled for data reading. During the data read process, the PREEN signal is set high to terminate charging of GBL and RBL. Simultaneously, N31 is turned on to initiate the comparison process for the sense amplifier. After WL0 is turned on, transistor N11 pulls down BL0. The BL0 signal is then transmitted to GBL through the transmission gate of multiplexer 200, coupling it to the input of sense amplifier N33. Simultaneously, DWL and WL0 are turned on simultaneously, and transistor N42 pulls down RBL through the already-enabled N41, coupling it to the input of sense amplifier N32.

[0084] The sense amplifier finally achieves rail-to-rail output. In the case of reading 0 (discharge process), the load of RBL in the reference circuit 400 is greater than the load of BL in the memory array 100, so the slope of RBL is greater than the slope of GBL, as shown in FIG. Figure 4 In the middle black and red line parts, during the same time, the voltage of RBL is greater than that of GBL, and the gate terminal voltage of N32 is greater than the gate terminal voltage of N33, making the voltage of node D slightly higher than that of C, and the voltage of node B higher than that of node A, causing P39 to turn on earlier than P38, further raising the voltage of node B to achieve rail-to-rail output: out1 outputs 1, and out2 outputs 0.

[0085] In the case of reading 1 (discharge process), RBL in the reference circuit 400 is in the process of reading 0, and the leakage rate of GBL must be smaller than that of RBL. Figure 4 In the middle black and blue line parts, the voltage of RBL is smaller than that of GBL in the same time, and the gate terminal voltage of N32 is smaller than the gate terminal voltage of N33, which makes the voltage of node D lower than that of C, and the voltage of node B is lower than that of node A. As a result, P39 is turned on later than P38, further lowering the voltage of node B to achieve rail-to-rail output: out1 outputs 0, and out2 outputs 1.

[0086] Rail-to-rail output refers to a device's output voltage being very close to the upper and lower limits of its input voltage, where "rail" refers to the circuit's input voltage. This circuit's rail-to-rail output utilizes positive feedback from the two first PMOS transistors (P38 and P39) and the two first NMOS transistors (N34 and N35) to amplify small input voltage differences. This structural characteristic ensures that the amplified voltage reaches the rail limits. Combined with a precharge device to eliminate intermediate interference, the output is ultimately stable at VDD or 0V. This characteristic is crucial for data comparison; only rail-to-rail output can clearly distinguish between "0" and "1," preventing reading errors.

[0087] As an optional solution, before the multiplexer 200 based on the storage circuit selects the storage cell to be read and the reading voltage of the bit line thereof, the method also includes: independently precharging the reference circuit 400 and the storage circuit through two independent precharging devices, wherein two precharging devices are provided, and the two precharging devices are respectively connected to the reference circuit 400 and the storage circuit.

[0088] If a pre-charge device is shared, the bit line of the storage circuit may be connected to multiple storage cells. The current fluctuation and charge transfer during pre-charge may interfere with the reference circuit 400 through the shared path; the pre-charge noise of the reference circuit 400 may also affect the pre-charge stability of the bit line of the storage circuit.

[0089] During independent pre-charging, the pre-charging paths of the two are completely isolated, and the load changes and charge fluctuations of the storage circuit will not be transmitted to the reference circuit 400, ensuring that the reference voltage always remains at a preset precise value, providing a reliable benchmark for subsequent sensing comparison.

[0090] Independent pre-charging can optimize parameters for the characteristics of the two respectively. The storage circuit aims at fast, stable and large capacitance, while the reference circuit 400 aims to accurately reach the benchmark value. This avoids slow pre-charging of the storage circuit due to shared pre-charging, which slows down the entire process, or overshoot of the reference circuit 400 due to high pre-charging current, thereby shortening the total time of the pre-charging stage and achieving the effect of improving the reading speed.

[0091] Independent pre-charging uses a physically isolated path to make the charges of the storage circuit bit line and the reference circuit 400 completely independent. Even if there is local leakage or noise, they will not affect each other, ensuring that both are in a stable initial voltage state when reading is started, reducing sensing errors caused by voltage drift and increasing ROM memory reading accuracy.

[0092] According to another aspect of the present invention, an electronic device is provided, comprising any one of the above-mentioned ROM memories.

[0093] ROM memory is an important type of non-volatile storage device in electronic devices. Non-volatility means that data is not lost after power failure. The characteristic of ROM memory is that once the information is written or preset at the factory, it can still be preserved for a long time after power failure. It is mainly used to read data during normal operation. Write operations are usually limited by factory programming, high-voltage programming, etc.

[0094] Factory programming refers to the process of programming or configuring electronic devices in a factory environment. High-voltage programming is a memory programming technology that primarily utilizes higher voltages to perform programming operations.

[0095] An embodiment of the present invention further provides a non-transitory machine-readable medium storing a computer program, wherein the computer program, when executed by a processor of a computer, is used to cause the computer to perform the method of the embodiment of the present invention.

[0096] The embodiments of the present invention further provide a computer program product, including a computer program, wherein the computer program, when executed by a processor of a computer, is used to cause the computer to execute the method of the embodiments of the present invention.

[0097] An embodiment of the present invention further provides an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor. The memory stores a computer program executable by the at least one processor, wherein the computer program, when executed by the at least one processor, causes the electronic device to perform the method of an embodiment of the present invention.

[0098] It should be noted that the term "including" and its variations used in the embodiments of the present invention are open inclusions, that is, "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; the term "some embodiments" means "at least some embodiments". The modifications of "one" and "multiple" mentioned in the embodiments of the present invention are illustrative and not restrictive. Those skilled in the art should understand that unless the context clearly indicates otherwise, they should be understood as "one or more".

[0099] The various steps described in the method implementation methods provided by the embodiments of the present invention may be performed in different orders and / or in parallel. In addition, the method implementation methods may include additional steps and / or omit the steps shown. The scope of protection of the present invention is not limited in this respect.

[0100] The term "embodiment" in this specification refers to specific features, structures or characteristics described in conjunction with the embodiment that can be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. The various embodiments in this specification are described in a related manner, and the same or similar parts between the various embodiments are referenced to each other. In particular, for the device, equipment, and system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts refer to the partial description of the method embodiment.

[0101] The above-described embodiments merely represent several implementation methods of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of protection. It should be noted that a person of ordinary skill in the art would be able to make various modifications and improvements without departing from the scope of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A ROM memory, characterized in that: Including: storage circuit, reference circuit, comparison circuit; The storage circuit includes a multiplexer and a storage array, and the storage array includes a plurality of storage cells arranged in an array; The reference circuit is used to generate a reference voltage based on a reference load during reading, wherein the reference load is greater than a minimum load of any bit line being read and less than a maximum load of any bit line being read, so that a voltage-time variation slope of the reference voltage is less than a voltage-time variation slope when a memory cell reads 0 and greater than a voltage-time variation slope when a memory cell reads 1, wherein the read bit line is a bit line corresponding to the multiplexer during reading; The two input terminals of the comparison circuit are respectively connected to the reference circuit and the storage circuit, and are used to compare the reference voltage and the read voltage to determine the corresponding output read digital signal, wherein the read voltage is the output voltage of the storage circuit when reading the data stored in the storage unit.

2. The ROM memory according to claim 1, wherein: The reference circuit includes the same number of first MOS transistors on the read bit line and a preset number of storage cells as reference cells; One end of the source or drain of the reference cell is connected to the bit line, and the other end is grounded, so that all the reference cells store 0; The enable signal of the gate of a memory cell in the reference cell is the corresponding virtual bit line, so that any corresponding bit line in the memory array is turned on and the virtual bit line is turned on; The gates of the remaining storage cells in the reference unit are all set to a low level to ensure that the storage cells are in a closed state.

3. The ROM memory according to claim 2, wherein: The preset number is greater than the number of storage units in the bit line, and the preset number is twice the number of storage units in the bit line.

4. The ROM memory according to claim 1, wherein: The reference circuit includes the same number of first MOS transistors on the read bit line and the same number of storage cells as reference cells; The enable signal of the gate of a memory cell in the reference cell is a corresponding virtual bit line, so that any corresponding bit line in the memory array is turned on, the virtual bit line is turned on, and one end of the source or drain of the memory cell is connected to the bit line and the other end is grounded, so that the reference cell stores 0; The sources or drains of the other storage cells in the reference cell are all connected to the bit line, so that the reference cell stores 1, and the gates are all set to a low level to ensure that the storage cell is in a closed state.

5. The ROM memory according to claim 1, wherein: Also included is a pre-charging device, the pre-charging device being connected to both the reference circuit and the storage circuit; There are two pre-charging devices, which are respectively connected to the reference circuit and the storage circuit.

6. The ROM memory according to claim 5, characterized in that The pre-charging device is a second PMOS tube; The gate of the second PMOS tube is connected to the pre-charge enable signal, the source of the second PMOS tube is connected to the high-voltage end, and the drain of the second PMOS tube is connected to the pre-charge circuit.

7. The ROM memory according to claim 1, wherein: The comparison circuit includes two second MOS tubes; The gates of the two second MOS transistors are respectively connected to the reference circuit and the storage circuit, the sources of the second MOS transistors are connected and then grounded through an NMOS transistor, the drains of the second MOS transistors are connected to the first NMOS transistor, and the drain output end of the first NMOS transistor is used to output the digital signal.

8. The ROM memory according to claim 7, wherein: The comparison circuit further includes two first PMOS transistors and two first NMOS transistors; The gate of the first PMOS transistor is connected to the drain of another first PMOS transistor, and the drain of the first PMOS transistor is connected to the drain of the corresponding first NMOS transistor; The gate of the first NMOS transistor is connected to the drain of another first NMOS transistor, and the source of the first NMOS transistor is connected to the drain of the corresponding second MOS transistor; And the drain of each of the first PMOS tube and the first NMOS tube is provided with an independent pull-up circuit.

9. The ROM memory according to claim 8, wherein: The comparison circuit is a sense amplifier.

10. A method for reading data from a ROM memory, characterized in that: include: Selecting a memory cell to be read and a read voltage of a bit line thereof based on a multiplexer of a memory circuit, wherein the memory circuit includes a multiplexer and a memory array, and the memory array includes a plurality of memory cells arranged in an array; Obtaining a reference voltage based on a reference circuit, wherein the reference circuit is configured to generate the reference voltage based on a reference load, wherein the reference load is greater than a minimum load of any read bit line and less than a maximum load of any read bit line, so that a voltage-time variation slope of the reference voltage is less than a voltage-time variation slope when a memory cell reads a value of 0 and greater than a voltage-time variation slope when a memory cell reads a value of 1, wherein the read bit line is a bit line corresponding to the multiplexer during reading; The reference voltage and the read voltage are input into a comparison circuit, and the comparison circuit outputs a corresponding read digital signal, wherein two input terminals of the comparison circuit are connected to the reference circuit and the storage circuit respectively.

11. The method according to claim 10, characterized in that Before a multiplexer based on a storage circuit selects a storage cell to be read and a voltage reading of a bit line thereof, the method further includes: The reference circuit and the storage circuit are independently precharged by independent precharging devices, wherein two precharging devices are provided and are connected to the reference circuit and the storage circuit respectively.

12. An electronic device, characterized in that: Comprising the ROM memory according to any one of claims 1 to 9.

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